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參數(shù)資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
13
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =
000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in
the sequence aborts the write to buffer operation. Please see Figure 7, Write to Buffer Flowchart for
additional information.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block while RP# is V
will fail.
11.Either 40H or 10H are recognized by the WSM as the byte/word program setup.
12.The clear block lock-bits operation simultaneously clears all block lock-bits.
13.Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
14.The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command
Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
15.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is
initiated.
4.1
Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to
read array mode. The read configuration register defaults to standard word/byte read mode. The
Read Array command also causes the device to enter read array mode. The device remains enabled
for reads until another command is written. Once the internal WSM has started a block erase,
program, or lock-bit configuration, the device will not recognize the Read Array command until
the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend
command. The Read Array command functions independently of the V
PEN
voltage.
4.2
Read Query Mode Command
This section defines the data structure or “database” returned by the Common Flash Interface (CFI)
Query command. System software should parse this structure to gain critical information such as
block size, density, x8/x16, and electrical specifications. Once this information has been obtained,
the software will know which command sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query is part of an overall specification for multiple
command set and control interface descriptions called Common Flash Interface, or CFI.
4.2.1
QUERY STRUCTURE OUTPUT
The Query “database” allows system software to gain information for controlling the flash
component. This section describes the device’s CFI-compliant interface that allows the host system
to access Query data.
Query data are always presented on the lowest-order data outputs (DQ
) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16
devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H
data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ
0-7
) and 00h in the high
byte (DQ
8-15
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F320J3A | 3 Volt Intel StrataFlash Memory(3 V 32M位英特爾StrataFlash存儲器) |
| 28F640J3A | 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器) |
| 28F128 | 3 Volt Intel StrataFlash Memory |
| 28F1602C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F3204C3 | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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