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參數(shù)資料
| 型號(hào)： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲(chǔ)器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲(chǔ)器（128兆位3伏地層的閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 15/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
9
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
Flash memories
allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5
Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID
string, system interface information, device geometry information, and Intel-specific extended
query information.
3.6
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code and the block lock
configuration codes for each block (see Figure 5). Using the manufacturer and device codes, the
system CPU can automatically match the device with its proper algorithms. The block lock
configuration codes identify locked and unlocked blocks.
3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection
and clearing of the status register, and, when V
PEN
= V
PENH
, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Block Lock-Bit commands require the command and block within the device to be
locked. The Clear Block Lock-Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE
, CE
, or CE
that disables the device (see Table 2,
Chip Enable
Truth Table
). Standard microprocessor write timings are used.
4.0
COMMAND DEFINITIONS
When the V
voltage
≤
V
, only read operations from the status register, query, identifier
codes, or blocks are enabled. Placing V
PENH
on V
PEN
additionally enables block erase, program, and
lock-bit configuration operations.
Device operations are selected by writing specific commands into the CUI. Table 4 defines these
commands.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
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