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參數(shù)資料
| 型號： | 28F128J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（128兆位3伏地層的閃速存儲器） |
| 文件頁數(shù)： | 33/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F128J3A |
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28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
27
NOTE:
When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse
width of 250 ns.
Table 17. Configuration Coding Definitions
Reserved
Pulse on
Program
Complete
(1)
Pulse on
Erase
Compete
(1)
bits 7—2
bit 1
bit 0
DQ
7–
DQ
2
= Reserved
DQ
1–
DQ
0
= STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse mode
such that the STS pin pulses low then high when the
operation indicated by the given configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits DQ
7–
DQ
2
to 00h) are as follows:
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
DQ
7–
DQ
2
are reserved for future use.
default (DQ
DQ
= 00) RY/BY#, level mode
— used to control HOLD to a memory controller to prevent
accessing a flash memory subsystem while any flash device's
WSM is busy.
configuration 01 ER INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has completed a Block Erase or sequence of
Queued Block Erases. Helpful for reformatting blocks after file
system free space reclamation or “cleanup”
configuration 10 PR INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has complete a Program operation. Provides
highest performance for servicing continuous buffer write
operations.
configuration 11 ER/PR INT, pulse mode
— used to generate system interrupts to trigger servicing of flash
arrays when either erase or program operations are completed
when a common interrupt service routine is desired.
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| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
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