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參數(shù)資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 98/161頁 |
| 文件大小： | 1832K |
| 代理商： | 28233-11 |
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3.0 Registers
CN8223
3.3 Configuration Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
3-12
Conexant
100046C
Octet/Cell
Handshake
Flag Threshold
0
1
1
01 (Single cell look- ahead)
1
10 or 11 (Normal mode)
0x2B
—
UTOPIA_1 (Utopia Port Control Register 1)
The UTOPIA_1 register is located at address 0x2B and controls operation of the UTOPIA interface. Operation
of the UTOPIA interface is detailed in
Section 2.7.5
.
Bit
Field
Size
Name
Description
15
–
7
9
Reserved
Set to 0.
6
1
Reset TX FIFO
Resets the address generators and flags associated with the transmit FIFO when
this bit is set high. This bit should be set high when Enable UTOPIA Interface (bit 0)
is first set high, then written low after ATM and PHY layer initialization is complete.
While the CN8223 is being initialized, its bit should be held low. Before setting this
bit high, the ATM layer UTOPIA interface control lines must be in an inactive state. If
they are not, the CN8223 UTOPIA FIFO pointers could become corrupted. To
conserve power, write this bit high if the UTOPIA interface is not used.
5
1
Reset RX FIFO
Resets the address generators and flags associated with the receive FIFO when this
bit is set high. This bit should be set high when the Enable UTOPIA Interface control
bit is first set high and can then be written low after ATM and PHY layer initialization
is complete. While the CN8223 is being initialized, this bit should be held low.
Before setting this bit high, the ATM layer UTOPIA interface control lines must be in
an inactive state. If they are not, the CN8223 UTOPIA FIFO pointers could become
corrupted. To conserve power, this bit should be written high if the UTOPIA
interface is not used.
4
1
Reserved
Set to 0.
3, 2
2
Flag Threshold
Selects the cell look-ahead level for asserting the TxFull~/TxClav flag to the ATM
layer. The control bits and flag look-ahead are as follows:
1
1
Octet/Cell
Handshake
Selects the full flag handshake protocol for the FIFO buffers. If this bit is low, then
octet-level handshaking is selected and the flags supplied are TxFull~ and
RxEmpty~. If this bit is high, then cell-level handshaking is selected, and the flags
supplied are TxClav and RxClav. In octet-handshake mode, the RxClav flag goes
active after one full cell is in the receive UTOPIA FIFO. Also in this mode, when the
256-byte transmit UTOPIA FIFO has 252 bytes filled, TxClav goes active, indicating
that only four bytes of space remain.
0
1
Enable UTOPIA
Interface
Selects the interface type on the FIFO I/O pins. If this bit is low, the interface is the
standard four-port FIFO interface. If this bit is high, then the interface is a
single-port UTOPIA-compliant interface controlled by the Port 0 Control Registers.
TxFull~/TxClav Look-Ahead
Full after 4 more octets
Full after current cell + 2 cells
Full after current cell + cell
Full after current cell
x
00 (Two-cell look-ahead)
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