參數(shù)資料
型號： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 138/161頁
文件大小： 1832K
代理商： 28233-11
4.0 Electrical and Mechanical Specifications
CN8223
4.3 Timing
ATM Transmitter/Receiver with UTOPIA Interface
4-4
Conexant
100046C
4.3 Timing
This section includes timing diagrams and descriptions for the CN8223.
4.3.1 Microprocessor Interface Timing
Table 4-2
and
Figure 4-1
display the timing requirements and characteristics of
the microprocessor interface. All times are in nanoseconds.
Table 4-2. Microprocessor Interface Timing
Name
Description
Min
Max
tprclk
Processor Clock Period
30
2X Cell Rate
tprh
Processor Clock Pulse Width High
10
—
tprl
Processor Clock Pulse Width Low
10
—
taspr
Address Strobe Setup to Processor Clock Rising Edge
4
—
tapr
Address Setup to Processor Clock Rising Edge
1
—
tcspr
Chip Select Setup to Processor Clock Rising Edge
4
—
tcsph
Chip Select to Processor Clock Rising Edge Hold Time
8
—
twpr
Write/Read Control Setup to Processor Clock Rising Edge
1
—
tpras
Address Strobe Hold after Processor Clock Rising Edge
tprh + 2 ns
tprl
–
4 ns
tdpr
Data Setup to Processor Clock Rising Edge (write cycle)
1.0
—
tprd
Data Hold after Processor Clock Rising Edge (write cycle)
3.0
—
todd
Output Enable Low to Data Bus Driven (read cycle)
1.5
6.0
todv
Output Enable Low to Data Bus Valid (read cycle)
1.6
6.0
todi
Output Enable High to Data Bus Invalid (read cycle)
1.3
4.9
todz
Output Enable High to Data Bus High-Z (read cycle)
1.4
5.1
tpdd
PRCLK High to Data Bus Driven (read cycle, OE~ low)
3.5
11.0
tpdv
PRCLK High to Data Bus Valid (read cycle, OE~ low)
3.6
11.0
tpdi
PRCLK high to Data Bus Invalid (read cycle, OE~ low)
3.2
10.0
tpdz
PRCLK High to Data Bus High-Z (read cycle, OE~ low)
3.2
10.0
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