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參數資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 70/161頁 |
| 文件大?。?/td> | 1832K |
| 代理商： | 28233-11 |
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Clock and control inputs consist of the following:
2.0 Functional Description
CN8223
2.6 ATM Cell Processing
ATM Transmitter/Receiver with UTOPIA Interface
2-36
Conexant
100046C
Each rising edge at the ONESECI input causes an indication in the
One-Second Count bit. This indication can be used as a timing interrupt to
coordinate status collection. If Enable One-second Latching of Line Status is set,
the ONESECI input also causes status indications in LINE_STATUS to be
latched. If an alarm condition is present during a one-second interval, it is
available to be read on the successive interval. Otherwise, the status is latched and
held until it is read. If this bit is set and the status word is read twice within a
one-second interval, the second read gives the current state of the status word and
clears the status register. Enable One-second Latching of Line Counters provides
the same functionality for the counters.
Each of the LINE_STATUS bits is latched until read and then cleared if the
condition is no longer present. If a status condition clears before the register is
read, the status bit is still held. Current status can be obtained by reading the
register twice in succession.
2.6.5 PLCP Transmit/Receive Synchronization
For 57-octet formats, the PLCP block must transmit segments at the same rate as
they are received. For DS1 and E1, long-term synchronization of the bit clock
rates establish this. For DS3 and E3 rates, the payload data rate is independent of
the line rate, and a separate timing/synchronization mechanism is required.
The DS3 and E3 PLCPs both have a 125 μs frame period. The reference clock
for this frame is taken from the received signal, or alternatively from an external
reference supplied to the 8 kHz clock input 8KCKI. In either case, the transmit
circuit generates one PLCP frame per reference frame.
In 53-octet formats, all frame structures are based on a 125
μ
s period;
consequently, no stuffing is required to synchronize the transmit and receive
segments.
An external 8 kHz reference for the PLCP at E3 and DS3
A one-second input to synchronize status collection timing in
multiple-port applications
A
“
hold receiver
”
input that can externally disable cell validation when an
external framer loses frame or signal
Three test inputs
A reset input
A one-second clock output is provided to allow synchronization of status
collection for multiple CN8223s or for CN8223s and framers. When a single
CN8223 is used, ONESECO should be connected to ONESECI. This timing
output is derived from the external 8 kHz reference clock input on 8KCKI.
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