參數(shù)資料
型號(hào)： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 95/161頁
文件大小： 1832K
代理商： 28233-11
CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.3 Configuration Control Registers
100046C
Conexant
3-9
Selects the active edge of the transmit clock output when connecting directly to an
external LIU. When this bit is low, the falling edge of TCLKO (or TCLKO_HS±) will be
centered on the relevant data outputs. When this bit is high, the rising edge of
TCLKO (or TCLKO_HS±) will be centered on the data outputs.
0x02
—
CONFIG_3 (Configuration Control Register 3)
The CONFIG_ 3 register is located at address 0x02 and controls miscellaneous functions.
Bit
Field
Size
Name
Description
15
–
12
4
Accept/Reject
Header
–
Port 3
–
0
Allows each receive port to be programmed to either accept or reject cells with
headers as specified in the RXHDR registers. When this bit is low, cells with
headers matching the header value (as qualified by the mask value) for the port will
be accepted and written out to the port. When this bit is high, cells with matching
headers (as qualified by the mask value) will be rejected, and all other cells will be
accepted and written out to the port.
11
1
Count Block Errors
Changes the count function of Error Counters 5
–
9 [0x44
–
0x48]. When this bit is
low, the counters count the actual number of errored bits in the BIP or FEBE octets.
When this bit is high, the counters increment once for each errored BIP or FEBE
block per G.826.
10
1
Reserved
Set to 0.
9
1
Line Loopback
Enables a loopback of the incoming receive data and clock to the transmit data and
clock outputs. The receive data is still processed by the receiver circuitry. Invert TX
Clock Output (bit 7) is functional in this mode to allow inversion of the looped clock
at TCLKO (or TCLKO_HS±). Line Loopback is not functional for TAXI or external
framer modes. Upon a hardware RESET (pin 118), this bit will be cleared (set to 0).
8
1
Invert RX Clock
Sampling
Selects the edge of the receive clock input where the incoming receive data is
sampled. When this bit is low, the incoming data on RXIN (or RXIN_HS±) is
sampled by the falling edge of RXCKI (or RXCKI_HS±). When this bit is high, the
incoming data is sampled on the rising edge. This bit must be set for operation in
TAXI mode.
7
1
Invert TX Clock
Output
6
1
For DS3 and G.751
E3 PLCP modes:
Force Nibble
Stuffing
If this bit is low, 13/14 nibble stuffing is performed in DS3 and G.751 E3 PLCP
modes. Stuffing is performed to synchronize the transmit PLCP with either the
external 8 kHz frame reference or the receive PLCP framer, depending on the setting
of External 8 kHz Timing in the CONFIG_1 register.
If this bit is high, the transmitter PLCP framing is allowed to free-run to an
internally generated 8 k frame rate when no clock is available from the 8 kHz input
or the receive PLCP framer. This bit is ignored in modes that do not perform nibble
stuffing.
6
1
For STS-3c and
STM-1 modes: Tx
Overhead Control
In STS-3c and STM-1 modes, this bit determines whether Transmit Overhead bytes
G1, K2#1, and Z2#3 are input from the Transmit Overhead bus or are internally
generated.
When this bit is set to 0 the following are internally generated:
G1-Path FEBE/RDI
—
Path FEBE is automatically generated in response to
Path BIP errors.
Path RDI (yellow alarm) is inserted according to CONFIG_5, bits 2 and 3.
K2#1
—
Line FERF is transmitted by setting CONFIG_2 bit 5 to a 1.
Z2#3
—
Line FEBE alarm is transmitted automatically in response to Line
BIP errors.
When this bit is set to 1, these bytes are obtained from the external TXOVH bus.
5
1
Parity Odd/Even
Set to 1: odd parity FIFO port generation and checking.
Set to 0: even parity FIFO port generation and checking.
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