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參數(shù)資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 105/161頁 |
| 文件大?。?/td> | 1832K |
| 代理商： | 28233-11 |
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CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.5 Receive Control Registers
100046C
Conexant
3-19
enabled with this bit, none of the other ports should be programmed for 53-octet
output.
3.5 Receive Control Registers
0x14
—
CELL_VAL (Cell Validation Control Register)
The CELL_VAL register is located at address 0x14. Validation checks performed by the validation process can
be individually disabled with the
“
Disable
”
control bits. These disable bits are global disables for all ports. Port
disables for payload length and payload CRC checks can also be found in CONFIG_4.
Bit
Field
Size
Name
Description
15
1
Start-of-Cell/Write
Error Output
Selects the function of the FCTRL_OUT[10] pin. When this bit is low, the output
indicates a FIFO write error. When this bit is high, the output is a start-of-cell
marker for the received cell data on the FIFO data port.
14
1
Disable Cell Receiver
Disables all cell validation and output after physical layer reception. This disable
control is internally synchronized to take effect on cell boundaries.
13
1
Enable Status Octet
Enables status output in 53-octet mode on port 3. See
Section 2.6
, for additional
information. When this bit is high, the HEC octet position in the FIFO output data is
omitted and a status word is appended to the end of the cell as octet number 53. In
53-octet cell formats, if status output is enabled with this bit, none of the other
ports should be programmed for 53-octet output.
12
1
Header Only Output
Enables a 5-octet output mode on port 3 only. See
Section 2.6
, for additional
information. Only the 4 header octets of cells addressed to port 3 and the status
octet are output to the FIFO port. In 53-octet cell formats, if status output is
11
1
Disable Payload CRC
Disables the payload CRC check. This disable controls only the output of cells to
the FIFO interface and does not control the counting of payload CRC errors. (This
applies for all ports.)
10
1
Disable Payload Len
Disables the payload length check. This disable controls only the output of cells to
the FIFO interface and does not control the counting of payload length errors. (This
applies for all ports.)
9
1
Disable HEC Check
Disables the check of the header error control octet. The CN8223 will pass cells
with HEC errors if this bit is set to 1. This bit is not functional in UTOPIA mode.
8
1
Enable HEC
Correction
Enables the HEC correction mode for single-bit header errors. If this bit is set to 0,
then no correction is performed but error detection is always performed. Error
correction must be disabled if HEC coverage is set for SMDS/802.6 mode or if
Enable HEC Coset (bit 0) in CONFIG_3 is not enabled.
7
–
6
2
Cell Output
Mode-Port 3
Number of ATM cell octets delivered to the FIFO interface.
00 - 48 Octets: Payload only mode
01 - 52 Octets: Header + Payload, no HEC
10 - 53 Octets: Header + HEC + payload
11 - 57 Octets: PLCP mode for all table entries
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