參數(shù)資料
型號： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 77/161頁
文件大小： 1832K
代理商： 28233-11
UTOPIA Signal
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.7 FIFO Port/UTOPIA Interface
100046C
Conexant
2-43
If Delete Idle Cells [bit 2] of CONFIG_4 [0x29] is set, then received cells
matching the idle header and mask criteria are automatically screened from
appearing on the output of all ports.
This idle cell screening is in addition to any reject values that are programmed
for the individual ports. Only addressed ports have active strobes.
2.7.5 UTOPIA Interface
The CN8223 incorporates an interface that is compliant with both the ATM
Forum
UTOPIA Level 1 (Version 2.01)
Specification and the Saturn Compliant
Interface for ATM PHY Devices Specification.
When the UTOPIA interface is enabled, the CN8223 becomes a single port
device with all input and output of cell data taking place on Port 0.
Configurations for ports 1, 2, and 3 (such as header values and masks or rate
controls) are ignored when in UTOPIA mode. The header values, masks, rate
controls, and other per-port configuration control bits for Port 0 govern the
operation of the UTOPIA port cell stream.
The UTOPIA interface contains transmit and receive buffer FIFOs with a
depth of four cells and is programmable for reduced latency requirements per
ATM Forum document 94/0317. UTOPIA interface pins are listed in
Table 2-27
.
The UTOPIA interface is controlled by
0x2B—UTOPIA_1 (Utopia Port
Control Register 1)
and
0x2C—UTOPIA_2 (Utopia Port Control Register 2)
. The
timing for the UTOPIA interface is functionally compatible with the timing
shown in the Version 2.01 ATM Forum Specification. Detailed timing
information can be found in
Chapter 4.0
.
Table 2-27. UTOPIA Interface Pins
CN8223 Pin
Signal Direction Relative to
CN8223
TxData (7:0)
FDAT_IN[7:0]
In
TxPrty 0
FDAT_IN[8]
In
TxSOC
FCTRL_IN[0]
In
TxEnb~
FCTRL_IN[1]
In
TxClk
FCTRL_IN[2]
In
TxFull~/TxClav
FCTRL_OUT[2]
Out
RxData (7:0)
FDAT_OUT[7:0]
Out
RxPrty 0
FDAT_OUT[8]
Out
RxSOC
FCTRL_OUT[0]
Out
RxEnb~
FCTRL_IN[3]
In
RxClk
FCTRL_IN[4]
In
RxEmpty~/RxClav
FCTRL_OUT[1]
Out
—
FCTRL_IN[5:7]
Reserved, Connect to Ground
—
FCTRL_OUT[16:4]
Undefined Output
RcvFifoOverflow
FCTRL_OUT[3]
Out
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