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參數(shù)資料
| 型號： | 28233-11 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | TRANSCEIVER, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 82/161頁 |
| 文件大小： | 1832K |
| 代理商： | 28233-11 |
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G.751 E3 N bit
G.832 E3 and E4 GC octet
STS-1/STS-3c/STM-1 D1, D2, D3 octet data link
2.0 Functional Description
CN8223
2.8 FEAC Channel and HDLC Data Link Programming
ATM Transmitter/Receiver with UTOPIA Interface
2-48
Conexant
100046C
2.8.3.4 Transmitter
Control Example
This example shows the sequence necessary to transmit a 10-byte hex message
starting in the low half of the transmit buffer. With the transmitter in the idle state,
the processor executes the following sequence:
write bytes 1 and 2 to address 0x5C
write bytes 3 and 4 to address 0x5D
write 19 to address 0x60 (bytes = 3, send message = 1)
at TX Interrupt:
write bytes 5 and 6 to address 0x5E
write bytes 7 and 8 to address 0x5F
write 39 to address 0x60 (bytes = 7, send message = 1)
at TX Interrupt:
write bytes 9 and 10 to address 0x5C
write 0B to address 0x60 (bytes = 1, send message = 1,
send FCS = 1)at TX Interrupt:
write 00 to address 0x60 (send message = 0, send FCS = 0
2.8.4 HDLC Data Link Receiver
The HDLC data link receiver is under the control of the received data stream only.
The receiver interrupt is under the control of Enable Receive Data Link Interrupt
[bit 7] in DL_CTRL_STAT [0x60]. You must enable this interrupt by setting this
bit for receiver interrupts to appear on the DL_INT output and for proper
interaction with the processor. The HDLC data link capability is present in the
following formats:
DS3 Terminal Data Link C bits
The data link bits are provided to the receiver circuitry at all times. Therefore,
when the LINE_STATUS register [0x38] indicates that alarms are being received
that render the data link information useless, you can disable the receive data link
interrupt to prevent excessive or spurious interrupts to the processor. Receiver
status is monitored via Receiver Interrupt [bit 15] in DL_CTRL_STAT and via
the receiver status bits in that register (bits 13-8). When a receive data link
interrupt is generated on DL_INT, the Receiver Interrupt bit is set. If this bit is
observed upon reading the DL_CTRL_STAT register, then the status obtained
from bits 13
–
8 indicates the receiver status that caused the interrupt.
The DL_CTRL_STAT register contains three status bits and a three-bit buffer
pointer. The status bits are Abort Flag Received [bit 8], Bad FCS [bit 9], and Idle
Code Received [bit 10]. The 3-bit buffer pointer RxBytes[2:0] [bits 13
–
11] is
used to point to locations in the 8-byte (organized as four 16-bit words)
RX_DL_BUFFER. This buffer is located at addresses 0x58 through 0x5B. The
buffer pointer indicates the last location written by the data link receiver. Byte 0
of the buffer is the least significant byte of 0x58, byte 1 is the most significant
byte of 0x58, byte 2 is the least significant byte of 0x59, etc.
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| 282-334 | 制造商:WAGO Innovative Connections 功能描述:End Plate 2 mm Thick-Color Grey For Use With Rail Mounted Terminal Block 制造商:WAGO 功能描述:GREY END PLATE 制造商:WAGO Innovative Connections 功能描述:END PLATE, 2MM, GREY; Series:-; Accessory Type:End Plate; For Use With:Rail Mounted Terminal Blocks ;RoHS Compliant: Yes |
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