參數(shù)資料
型號： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 28/161頁
文件大?。?/td> 1832K
代理商： 28233-11
1.0 Product Description
CN8223
1.9 Logic Diagram
ATM Transmitter/Receiver with UTOPIA Interface
1-18
Conexant
100046C
Figure 1-11. CN8223 Logic Diagram
Receive Clock Input
Receive Clock In PECL
Receive Serial In PECL
Receive Input
Transmit Clock Input
Transmit Clock In PECL
Transmit Input
Transmit Overhead
FIFO Data Bus In
FIFO Control Input
8 kHz Clock Input
One-Second Clock Sync
Receiver Hold Input
Test Input
Test Inputs
Reset
Processor Clock
Chip Select
Address Strobe
Write/Read Control
Output Enable
Processor Data Bus
Address Bus
8/16-Bit Mode Select
Bus In
98
–
105,
108
109
–
116
Microprocessor
Interface
Transmit Clock Output
Transmit Outputs
Transmit Clock Out PECL
Transmit Serial Out PECL
Loss of Cell Delineation
RXCKI
RXCKI_HS
±
RXIN_HS
±
RXIN[8:0]
TXCKI
TXCKI_HS
±
TXIN
TCLKO
TXOUT[8:0]
TCLKO_HS
±
TXOUT_HS
±
LOCD
Line Framer/PHY
Interface
I
I
I
I
I
I
I
TXOVH[7:0]
I
O
O
O
O
O
Framing Overhead
Interface
O
O
O
O
O
Receive Overhead Bus Out
Receive Overhead Markers
Receive Overhead Clocks
Transmit Overhead Clock
Transmit Overhead Marker
RXOVH[7:0]
RMRKR[1:0]
ROVH_CLK[1:0]
TOVH_CLK
TMRKR
FDAT_IN[8:0]
FCTRL_IN[7:0]
I
I
UTOPIA/FIFO
Interface
FDAT_OUT[8:0]
FCTRL_OUT[16:0]
O
O
FIFO Data Bus Out
FIFO Control Outputs
I
I
I
I
I
I/O
I
PRCLK
CS
~
AS
~
W/R
~
OE
~
D[15:0]
A[7:1]
DL_INT
STAT_INT
O
O
FEAC/HDLC Interrupt
Status/Counter Interrupt
8KCKI
ONESECI
RCV_HLD
NTEST
TEST1, TEST3
RESET
I
I
I
I
I
I
Clock and Control
O One-Second Output
ONESECO
15
–
19,
154,155
22,25
10
11,12
20,21
30
31
33
–
36,
42,43,
56
–
58
28,29
38,39
122
156
–
159
8,9
6,7
55
52
2
–
5,
23,24
32
44
–
51
I
37
97
96
94
95
92
65,
SEL8BIT
82
–
84
85
–
91
62
61
123
59
119
118
143
–
145,
148
–
153
124
–
132,
135
–
142
63
64
60
68
–
79,
117,
I = Input, O = Output
8
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