
μ
PD30102
53
Preliminary Data Sheet
8. CMU (CLOCK MASK UNIT)
8.1 General
The CMU is used to specify whether the CPU core supplies the clock to each peripheral unit. By supplying the clock
only to the necessary peripheral units, the power consumption can be reduced.
Table 8-1. CMU Register
Physical Address
Symbol
Function
0x0B00 0060
CMUCLKMSK
CMU clock mask register
9. ICU (INTERRUPT CONTROL UNIT)
9.1 General
The ICU receives an interrupt request signal from each peripheral unit and generates an interrupt request signal
(Int0, Int1, Int2, Int3, or NMI) to the CPU core.
The function overview of ICU internal block is shown below.
Table 9-1. ICU Registers
Physical Address
Symbol
Function
0x0B00 0080
SYSINT1REG
System interrupt register1 (level 1)
0x0B00 0082
PIUINTREG
PIU interrupt register (level 2)
0x0B00 0084
AIUINTREG
AIU interrupt register(level 2)
0x0B00 0086
KIUINTREG
KIU interrupt register (level 2)
0x0B00 0088
GIUINTLREG
GIU interrupt low-order address register (level 2)
0x0B00 008A
DSIUINTREG
DSIU interrupt register (level 2)
0x0B00 008C
MSYSINT1REG
System interrupt mask register 1 (level 1)
0x0B00 008E
MPIUINTREG
PIU interrupt mask register (level 2)
0x0B00 0090
MAIUINTREG
AIU interrupt mask register (level 2)
0x0B00 0092
MKIUINTREG
KIU interrupt mask register (level 2)
0x0B00 0094
MGIUINTLREG
GIU interrupt mask low-order address register (level 2)
0x0B00 0096
MDSIUINTREG
DSIU interrupt mask register (level 2)
0x0B00 0098
NMIREG
Battery interrupt select register
0x0B00 009A
SOFTINTREG
Software interrupt register
0x0B00 0200
SYSINT2REG
System interrupt register 2 (level 1)
0x0B00 0202
GIUINTHREG
GIU interrupt high-order address register (level 2)
0x0B00 0204
FIRINTREG
FIR interrupt register (level 2)
0x0B00 0206
MSYSINT2REG
System interrupt mask register 2 (level 1)
0x0B00 0208
MGIUINTHREG
GIU interrupt mask high-order address register (level 2)
0x0B00 020A
MFIRINTREG
FIR interrupt mask register (level 2)