參數(shù)資料
型號： μPD30102
廠商： NEC Corp.
英文描述： 64-/32-BIT Microprocessor(64/32位微處理器)
中文描述： 64-/32-BIT微處理器（64/32位微處理器）
文件頁數(shù)： 25/112頁
文件大?。?/td> 639K
代理商： ΜPD30102
μ
PD30102
25
Preliminary Data Sheet
3.2 CPU Registers
Figure 3-2 shows the CPU registers of the V
R
4102. The bit width of these registers is determined by the operation
mode of the processor (32 bits in 32-bit mode or 64 bits in 64-bit mode).
Of the 32 general-purpose registers, the following two have a special meaning.
Register r0
: The contents of this register are always 0. To discard the result of an operation, describe this
register as the target of an instruction. When value 0 is necessary, this register can also be
used as a source register.
Register r31 : This is a link register used by link instructions, such as the Jump and Link (JAL) instruction.
r31 can be used by other instructions. However, be careful that use of the register by a link
instruction will not coincide with use of the register for other operations.
The two multiplication/division registers (HI and LO) store the result of multiplication or sum-of-products operation, or
quotient (LO) and remainder (HI) resulting from division.
Because the V
R
4102 does not support floating-point instructions, it is not provided with the 32 floating-point general-
purpose registers (FGR) found in the V
R
4300 and V
R
4400.
Remark
The load link bit (LL bit) used with synchronization instructions (LL and SC) for multiprocessor
supported by the V
R
4300 and V
R
4400 is not provided in the V
R
4102 (refer to
3.3 (2) Deletion of
multiprocessor instructions
).
Figure 3-2. CPU Registers
63
32 31
r0 = 0
32 31
0
63
0
r2
HI
r1
r29
r30
r31= LinkAddress
·
·
·
·
LO
PC
63
32 31
0
63
32 31
0
Program counter
Multiplication/division registers
General-purpose registers
The V
R
4102 does not have a program status word (PSW). The function of PSW is substituted by the status registers
and cause registers incorporated to the system control coprocessor (CP0).
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