參數(shù)資料
型號: μPD30102
廠商: NEC Corp.
英文描述: 64-/32-BIT Microprocessor(64/32位微處理器)
中文描述: 64-/32-BIT微處理器(64/32位微處理器)
文件頁數(shù): 30/112頁
文件大?。?/td> 639K
代理商: ΜPD30102
μ
PD30102
30
Preliminary Data Sheet
3.5 Data Format and Addressing
The V
R
4102 uses the following four data formats:
Double word (64 bits)
Word (32 bits)
Half word (16 bits)
Byte (8 bits)
The byte ordering is set by the BE bit of the config register. With the current V
R
4102, set little endian.
The byte ordering (endian) can be inverted during operation by setting the RE bit of the status register. However, be
sure not to set this to 1 with the current V
R
4102.
Figure 3-5. Byte Address in Word: Little Endian
31
24 23
16 15
0
High-order
address
Low-order
address
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word
address
12
8
4
0
8 7
Remarks 1.
The least significant byte is the lowest address.
2.
A word is addressed by the address of the least significant byte.
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