參數(shù)資料
型號(hào): μPD30102
廠商: NEC Corp.
英文描述: 64-/32-BIT Microprocessor(64/32位微處理器)
中文描述: 64-/32-BIT微處理器(64/32位微處理器)
文件頁(yè)數(shù): 35/112頁(yè)
文件大小: 639K
代理商: ΜPD30102
μ
PD30102
35
Preliminary Data Sheet
Figure 3-11. Outline of Address Translation
y+8
y+1 y
x+1 x
0
x–1
31
0
ASID
VPN
Offset
Virtual address
<1>
<2>
<3>
Selector
<4>
31
x x–1
0
TLB
x = 10, 12, 14, 16, 18
y = 31 (in 32-bit mode)
63 (in 64-bit mode)
Physical address
<1> A virtual address page number (VPN) is
compared with VPN in TLB.
<2> If the two VPNs coincide, a page frame
number (PFN) indicating the high-order
bits of a physical address is output to
the selector.
<3> If the low-order 1 bit of VPN is 0, an even
page is selected; if it is 1, an odd page is
selected. The selected page is output to
the high-order bits of the physical address.
<4> The offset is output to the low-order bits of
the physical address without going through
TLB.
The TLB entry is read or written by loading/storing among the TLB entry indicated by the index register and random
register, entry Hi, entry Lo1, entry Lo0, and page mask registers.
How the TLB is manipulated is illustrated below.
Figure 3-12. Outline of TLB Manipulation
Entry Lo0 register
Page mask register
Entry Lo1 register
Entry Hi register
Index register
Random register
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