參數(shù)資料
型號(hào)： μPD30102
廠商： NEC Corp.
英文描述： 64-/32-BIT Microprocessor(64/32位微處理器)
中文描述： 64-/32-BIT微處理器（64/32位微處理器）
文件頁數(shù)： 12/112頁
文件大?。?/td> 639K
代理商： ΜPD30102
μ
PD30102
12
Preliminary Data Sheet
(2/2)
Signal Name
LCAS#
I/O
O
Function
This is the DRAM’s CAS signal. This signal is active when a valid column address
is output via the ADD bus during access of DATA (0:7) in the DRAM.
BUSCLK
O
This is the system bus clock. It is used to output the clock that is supplied to the
controller on the system bus.
The frequency to be output is determined according to the state of pins CLKSEL2/TxD,
CLKSEL1/RTS#, and CLKSEL0/DTR#.
(See
(5) RS-232C interface signals
)
SHB#
O
This is the system bus high-byte enable signal. During system bus access, this signal
is active when the high-order byte is valid on the data bus.
IOR#
O
This is the system bus I/O read signal. It is active when the V
R
4102 accesses the
system bus to read data from an I/O port.
IOW#
O
This is the system bus I/O write signal. It is active when the V
R
4102 accesses the
system bus to write data to an I/O port.
MEMR#
O
This is the system bus memory read signal. It is active when the V
R
4102 accesses the
system bus to read data from memory.
MEMW#
O
This is the system bus memory write signal. It is active when the V
R
4102 accesses
the system bus to write data to memory.
ZWS#
I
This is the system bus zero wait state signal. Set this signal as active to enable the
controller on the system bus to be accessed by the V
R
4102 without a wait interval.
RSTOUT
O
This is the system bus reset signal. It is active when the V
R
4102 resets the system
bus controller.
MEMCS16#
I
This is a dynamic bus sizing request signal.
Set this signal as active when system bus memory accesses data in 16-bit width
(however, the DRAM bus memory space that is controlled by the DBUS32 pin is
excepted).
IOCS16#
I
This is a dynamic bus sizing request signal.
Set this signal as active when system bus I/O accesses data in 16-bit width.
IOCHRDY
I
This is the system bus ready signal. Set this signal as active when the system bus
controller is ready to be accessed by the V
R
4102.
HLDRQ#
I
This is a hold request signal for the system bus and DRAM bus that is sent from an
external bus master.
HLDACK#
O
This is a hold acknowledge signal for the system bus and DRAM bus that is sent to
an external bus master.
DBUS32/GPIO48
I/O
This function differs depending on how the RTCRST# pin is set.
<When RTCRST# = 1>
This can be used as a general-purpose output port.
<When RTCRST# = 0>
This can be used as the data-bus width switch signal. The data is sampled while the
RTCRST# signal is low, and is retained while the RTCRST3 signal is high.
1: Data bus is used in 32-bit width
0: Data bus is used in 16-bit width
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