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參數(shù)資料
| 型號(hào)： | μPD30102 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT Microprocessor(64/32位微處理器) |
| 中文描述： | 64-/32-BIT微處理器（64/32位微處理器） |
| 文件頁數(shù)： | 11/112頁 |
| 文件大?。?/td> | 639K |
| 代理商： | ΜPD30102 |
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μ
PD30102
11
Preliminary Data Sheet
1. PIN FUNCTIONS
Remark
# indicates active low.
1.1 Pin Functions
(1) System bus interface signals
(1/2)
Signal Name
I/O
Function
ADD (0:25)
O
This is a 25-bit address bus. Used to specify addresses of the V
R
4102, DRAM, ROM,
LCD, and system bus (ISA).
DATA (0:15)
I/O
This is a 16-bit data bus. Used to transfer data from the V
R
4102 to DRAM, ROM, LCD,
and system bus, and vice versa.
DATA (16:31)/
GPIO (16:31)
I/O
This function differs depending on how the DBUS32 pin is set.
<When DBUS32 = 1>
It is the high-order 16 bits of the 32-bit data bus.
This bus is used for transmitting and receiving data between the V
R
4102 and the DRAM
and ROM.
<When DBUS32 = 0>
It is a general-purpose I/O (GPIO) port.
LCDCS#
O
This is the LCD chip select signal. This signal is active when the V
R
4102 is performing
LCD access using the ADD/DATA bus.
RD#
O
Active when the V
R
4102 is reading data from the LCD, RAM, or ROM.
WR#
O
Active when the V
R
4102 is writing data to the LCD, RAM, or ROM.
LCDRDY
I
This is the LCD ready signal. Set this signal as active when the LCD controller is ready
to be accessed from the V
R
4102.
ROMCS (0:3)#
O
This is the ROM chip select signal. It is used to select a ROM to be accessed from
among up to four connected ROM units.
UUCAS#/
MRAS3#
O
This function differs depending on how the DBUS32 pin is set.
<When DBUS32 = 1>
UUCAS#
This signal is active when a valid column address is output via the ADD bus during
access of DATA (24:31) in the 32-bit data bus.
<When DBUS32 = 0>
MRAS3#
This is the DRAM’s RAS signal. Up to four DRAM units can be connected, and this
signal is active when a valid row address is output via the ADD bus for the DRAM
connected to the high-order address.
ULCAS#/
MRAS2#
O
This function differs depending on how the DBUS32 pin is set.
<When DBUS32 = 1>
ULCAS#
This signal is active when a valid column address is output via the ADD bus during
access of DATA (16:23) in the 32-bit data bus.
<When DBUS32 = 0>
MRAS2#
This is the DRAM’s RAS signal. This signal is active when a valid row address is output
via the ADD bus for the DRAM connected to the next-highest address after the highest
high-order address.
MRAS (0:1)#
O
This is the DRAM’s RAS-only signal.
UCAS#
O
This is the DRAM’s CAS signal. This signal is active when a valid column address
is output via the ADD bus during access of DATA (8:15) in the DRAM.
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