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參數(shù)資料
| 型號(hào)： | μPD30102 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT Microprocessor(64/32位微處理器) |
| 中文描述： | 64-/32-BIT微處理器（64/32位微處理器） |
| 文件頁(yè)數(shù)： | 45/112頁(yè) |
| 文件大?。?/td> | 639K |
| 代理商： | ΜPD30102 |
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μ
PD30102
45
Preliminary Data Sheet
4.1.2 RSTSW
Assert the RSTSW# pin active.
Reset by RSTSW initializes all the internal statuses except the RTC timer and PMU. Because the DRAM does not
enter the self-refresh mode, the contents of the DRAM after RSTSW reset are not guaranteed.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4102 is reset, completely initialize the processor in software.
Figure 4-2. RSTSW
RSTSW# (input)
ColdReset# (internal)
MRAS (0 : 3)# (output)
UCAS#/LCAS# (output)
L
H
POWER (input)
MPOWER (input)
Reset# (internal)
PLL (internal)
RTC
(internal, 32 kHz)
Stable oscillation
Stable oscillation
Stable oscillation
Undefined
> 3RTC
16 ms
16 MasterClock
Note
Note
MasterClock is the basic clock in the CPU core.
4.1.3 Deadman’s SW
The V
R
4102 is reset if Deadman’s SW is not cleared within a specific time after Deadman’s SW was enabled.
Reset by Deadman’s SW initializes all the internal statuses except the RTC timer and PMU. Because the DRAM
does not enter the self-refresh mode, the contents of the DRAM after Deadman’s SW reset are not guaranteed. For the
setting of Deadman’s SW, see
12. DSU (Deadman’s SW Unit)
.
After reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is
executed, and accessing the reset vector in the ROM space is started. Because only part of the internal status of the
V
R
4102 is reset, completely initialize the processor in software.
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