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參數(shù)資料
| 型號： | μPD30102 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT Microprocessor(64/32位微處理器) |
| 中文描述： | 64-/32-BIT微處理器（64/32位微處理器） |
| 文件頁數(shù)： | 26/112頁 |
| 文件大小： | 639K |
| 代理商： | ΜPD30102 |
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μ
PD30102
26
Preliminary Data Sheet
3.3 Outline of Instruction Set
Basically, the instruction set of the V
R
4102 conforms to the MIPS-I, -II, and -III instruction sets. However, it is different
from those of the other processors in the V
R
series in the following four points. The difference between the V
R
4100 and
V
R
4102 is that the V
R
4102 can manage operations including the peripheral functions by using power mode instructions
(refer to
(4)
).
(1) Deletion of floating-point (FPU) instructions
Because the V
R
4102 does not have a floating-point unit, it does not support FPU instructions. If an FPU
instruction is encountered, therefore, a reserved instruction exception occurs. If it is necessary to use an
FPU instruction, emulate the instruction in software in an exception handler.
(2) Deletion of multiprocessor instructions
The V
R
4102 does not support a multiple processor operating environment. If a synchronization support
instruction (LL or SC instruction) defined by MIPS-II and -III ISA is encountered, a reserved instruction
exception occurs. In addition, the load link bit (LL bit) is also unavailable.
The V
R
4102 executes all load/store instructions in the programmed sequence. Therefore, the SYNC
instruction is treated as a NOP instruction.
(3) Addition of sum-of-products instructions
The V
R
4102 has a dedicated sum-of-products operation core in the CPU and additional integer sum-of-
products operation instructions, in order to execute sum-of-products operation at high speeds. Note that
these instructions are not correctly executed with any other processors in the V
R
series.
The operations by the sum-of-products instructions are as follows:
(a) MADD16 (Multiply and Add 16-bit Integer)
This instruction multiplies the contents of general-purpose register rs by the contents of general-purpose
register rt. Both the operands are treated as signed 16-bit integers. Bits 62 through 15 of both the
operands must be sign-extended.
The result of the multiplication is added to a 64-bit value combining special registers HI and LO. The
low-order word (64 bits) of the result is loaded to special register LO, and the high-order word is loaded
to HI.
An integer overflow exception does not occur.
Figure 3-3 outline the operation of the MADD16 instruction.
Figure 3-3. Operation of MADD16 Instruction
rs
rt
31
15
General-purpose register file
MUL
ADD
HI
LO
63
31
High-order
Low-order
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