參數(shù)資料
型號: μPD30102
廠商: NEC Corp.
英文描述: 64-/32-BIT Microprocessor(64/32位微處理器)
中文描述: 64-/32-BIT微處理器(64/32位微處理器)
文件頁數(shù): 51/112頁
文件大?。?/td> 639K
代理商: ΜPD30102
μ
PD30102
51
Preliminary Data Sheet
6. DMAAU (DMA ADDRESS UNIT)
6.1 General
DMAAU controls the addresses for the DMA operations between AIU/IrDA 4-Mbyte communication module (FIR) and
memory.
The DMA start address of each DMA channel can be specified in a range of 0x0000 0000 through 0x01FF FFFE as
a half-word address. The DMA space of each DMA channel is secured in a 2-Kbyte block that starts from the address
generated by masking lower ten bits of the DMA start address to zero.
The DMA operation is not guaranteed if the DMA space overlaps with that of other peripheral units.
Table 6-1. DMAAU Registers
Physical Address
Symbol
Function
0x0B00 0020
AIUIBALREG
DMA base low-order address register for AIU input
0x0B00 0022
AIUIBAHREG
DMA base high-order address register for AIU input
0x0B00 0024
AIUIALREG
DMA low-order address register for AIU input
0x0B00 0026
AIUIAHREG
DMA high-order address register for AIU input
0x0B00 0028
AIUOBALREG
DMA base low-order address register for AIU output
0x0B00 002A
AIUOBAHREG
DMA base high-order address register for AIU output
0x0B00 002C
AIUOALREG
DMA low-order address register for AIU output
0x0B00 002E
AIUOAHREG
DMA high-order address register for AIU output
0x0B00 0030
FIRBALREG
DMA base low-order address register for FIR
0x0B00 0032
FIRBAHREG
DMA base high-order address register for FIR
0x0B00 0034
FIRALREG
DMA low-order address register for FIR
0x0B00 0036
FIRAHREG
DMA high-order address register for FIR
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