參數(shù)資料
型號(hào)： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 90/105頁(yè)
文件大?。?/td> 1307K
代理商： XRT72L73
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC
REV. P1.0.1
á
PRELIMINARY
90
T
ABLE
97:
T
X
CP C
ONTROL
R
EGISTER
R
EGISTER
96 T
X
CP C
ONTROL
R
EGISTER
H
EX
A
DDRESS
: 0
X
60
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Scrambler Enable
R/W
1
0: Disables scrambling of payload bits
1: Enables scrambling of payload bits
6
Coset Enable
R/W
1
0: Disables addition of Coset Polynomial to HEC byte
1: Enables addition of Coset Polynomial to HEC byte
5
Valid Cell HEC Insert
Enable
R/W
1
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” valid ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
N
OTES
:
1. This register bit-field only applies to Valid (e.g., User and OAM)
cells.
2. This bit-field is only active if the XRT72L73 is configured to operate
in the “ATM UNI” mode.
4
TDP Check Pattern
R/W
1
0: An Alternating 0x55/0xAA pattern is expected (as the “Data Path Integrity
Check byte) in the fifth octet position, within each Valid cell that is processed
by the Transmit Cell Processor.
1: A constant 0x55 pattern is expected (as the “Data Path Integrity Check”
byte) in the fifth octet position, within each Valid cell that is processed by the
Transmit Cell Processor.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to operate
in the “ATM UNI” Mode.
3
GFC Insert Enable
R/W
0
0: The “GFC Input Port” is disabled.
1: The “GFC Input Port” is enabled. Data is read via TxGFC serial input pin
and is inserted into GFC nibble-field within of each “outbound” ATM cell.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to operate
in the “ATM UNI” Mode.
2
TDP Error Interrupt Enable
R/w
0
0: Disables the “Data Path Integrity Check” interrupt.
1: Enables the “Data Path Integrity Check” interrupt.
1
Idle Cell HEC Insert Enable
R/w
1
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” Idle ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
N
OTES
:
1. This register bit-field only applies to Idle cells.
2. This bit-field is only active if the XRT72L73 is configured to operate
in the “ATM UNI” mode.
0
TDP Error Interrupt Status
RUR
0
0: Indicates that the “Data Path Integrity Check” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Data Path Integrity Check” Interrupt has occurred since
the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to
operate in the “ATM UNI” Mode.
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