XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.1
á
PRELIMINARY
18
D20
B19
A19
Req_0
Req_1
Req_2
O
Receive Equalization Bypass Control Output Pin—(to be connected to the
XRT73L03 E3/DS3/STS-1 LIU IC):
This output pin is intended to be connected to the Req input pin of the XRT73L03 E3/
DS3/STS-1 LIU IC. The user can control the state of this output pin by writing a ‘0’
or ‘1’ to Bit 5 (Req ) of the Line Interface Driver Register (Address = 0x72). If the
user commands this signal to toggle “High” then it will cause the incoming DS3 line
signal to “by-pass” equalization circuitry, within the XRT73L03 Device. Conversely,
if the user commands this output signal to toggle “Low”, then the incoming DS3
line signal with be routed through the equalization circuitry. For information on the
criteria that should be used when deciding whether to bypass the equalization cir-
cuitry or not, please consult the “XRT73L03 E3/DS3/STS-1 LIU IC” data sheet.
Writing a “1” to Bit 5 of the Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause this
output pin to toggle “Low”.
N
OTE
:
If the designer is not using the XRT73L03 E3/DS3/STS-1 LIU IC, then this
output pin can be used for other purposes.
P23
N24
N25
RLOL_0
RLOL_1
RLOL_2
I
Receive Loss of Lock Indicator—from the XRT73L03 E3/DS3/STS-1 LIU IC:
This input pin is intended to be connected to the RLOL (Receive Loss of Lock) out-
put pin of the XRT73L03 LIU IC. The user can monitor the state of this pin by read-
ing the state of Bit 1 (RLOL) within the Line Interface Scan Register (Address =
0x73). If this input pin is “Low”, then it means that the phase-locked-loop circuitry,
within the XRT73L03 is properly locked onto the incoming DS3 data-stream; and is
properly recovering clock and data from this DS3 data-stream. However, if this
input pin is “High”, then it means that the phase-locked-loop circuitry, within the
XRT73L03 has lost lock with the incoming DS3 data-stream, and is not properly
recovering clock and data.
For more information on the operation of the XRT73L03 E3/DS3/STS-1 LIU IC,
please consult the "XRT73L03 E3/DS3/STS-1 LIU IC" data sheet.
N
OTE
:
If the designer is not using the XRT73L03 DS3/E3/STS-1 LIU IC, this input
pin can be used for other purposes.
A15
B14
A14
RLOOP_0
RLOOP_1
RLOOP_2
O
Remote Loop-back Output Pin (to the XRT73L03 DS3/E3/STS-1 LIU IC):
This output pin is intended to be connected to the RLOOP input pin of the
XRT73L03 LIU IC. This output pin, along with the LLOOP input pin permits the user
to configure the XRT73L03 to operate in either of the following three (3) loop-back
modes.
Analog Local Loop-Back Mode
Digital Local Loop-Back Mode
Remote Loop-Back Mode.
Writing a “1” to bit 1 of the “Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause the
RLOOP output to toggle “Low”.
N
OTE
:
If the customer is not using the XRT73L03 DS3/E3/STS-1 IC, then this out-
put pin can be used for other purposes.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION