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參數(shù)資料
| 型號： | XRT72L73 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 21/105頁 |
| 文件大小： | 1307K |
| 代理商： | XRT72L73 |
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XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
21
A8
C7
B7
TxFrameRef_0
TxFrameRef_1
TxFrameRef_2
I
Transmit DS3 Framer—Frame Reference Input Pin:
The Transmit DS3 Framer can be configured to use this input signal as the “framing”
reference for the Transmit DS3 Framer block. If this input pin is chosen to be the
timing reference, then any rising edge at this input will cause the Transmit DS3
Framer to begin its creation a new DS3 M-frame. Consequently, the user must
supply a clock signal that is equivalent to the DS3 Frame rate (or 9398.3 Hz). Fur-
ther, the signal which is driving this input pin, must be synchronized witht he
44.736MHz clock signal, which is applied to the “TxInClk” input pin.
N
OTE
:
This input pin should be tied to “GND” if it is not used as the Transmit DS3
Framer frame reference signal.
Transmit DS3 Framer Block—Clock Signal:
The Transmit DS3 Framer can be configured to use this input signal as the timing
reference. If this input pin is chosen to be the timing reference, then the user must
supply a "High" quality 44.736 MHz signal to this input pin. In this configuration,
frame generation, by the Transmit DS3 Framer, will be asynchronous (with any
other timing signals within the UNI). However, frame timing will be based upon this
clock signal.
N
OTE
:
This input pin should be tied to “GND” if it is not used as the Transmit DS3
Framer timing reference.
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Unit, along with the TxPOS and
TxNEG signals. The purpose of this output clock signal is to provide the LIU with
timing information that it can use to generate the AMI pulses and deliver them over
the transmission medium to the Far-End Receiver. The user can configure the
source of this clock to be either the RxLineClk (from the Receiver portion of the UNI)
or the TxIineClk input. The nominal frequency of this clock signal is 44.736 MHz.
C2
D7
D16
TxInClk_0
TxInClk_1
TxInClk_2
I
E4
G4
F2
TxLineClk_0
TxLineClk_1
TxLineClk_2
O
D1
C8
C14
TxNEG_0
TxNEG_1
TxNEG_2
O
Transmit Negative Polarity Pulse:
The exact role of this output pin depends upon whether the UNI is operating in the
Unipolar or Bipolar Mode.
Unipolar Mode:
This output signal pulses “High” for one bit period, at the end of each “outbound”
DS3 frame. This output signal is at a logic “Low” for all of the remaining bit-periods
of the “outbound” DS3 frames.
Bipolar Mode:
This output pin functions as one of the two dual-rail output signals that commands
the sequence of pulses to be driven on the line. TxPOS is the other output pin.
This input is typically connected to the TNDATA input of the external DS3 Line
Interface Unit IC. When this output is asserted, it will command the LIU to generate
a negative polarity pulse on the line.
F3
F1
G3
TxOH_0
TxOH_1
TxOH_2
I
Transmit Overhead Input Pin
The Transmit Overhead Data Input Interface accepts the overhead data via this
input pin, and inserts into the "overhead" bit position within the very next "out-
bound" DS3 frame. If the "TxOHIns" pin is pulled "High", the Transmit Overhead
Data Input Interface will sample the data at this input pin (TxOH), on the falling
edge of the "TxOHClk" output pin. Conversely, if the "TxOHIns" pin is pulled "Low",
then the Transmit Overhead Data Input Interface will NOT sample the data at this
input pin (TxOH). Consequently, this data will be ignored.
B6
A6
C5
TxOHClk_0
TxOHClk_1
TxOHClk_2
O
Transmit Overhead Clock:
The function of this pin is the same in both Clear Channel and ATM UNI Modes of
the XRT72L73. This pin serves as the clock signal for the external interface to
insert the OH data on the TxOH pin. The user can insert OH data on the TxOH pin
at the rising edge of this clock signal.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT72L74 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT7300IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7302 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L02M | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7300IV | 功能描述:外圍驅(qū)動器與原件 - PCI . . RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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