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參數(shù)資料
| 型號： | XRT72L73 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 6/105頁 |
| 文件大小： | 1307K |
| 代理商： | XRT72L73 |
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XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC
REV. P1.0.1
á
PRELIMINARY
6
a DS3 data stream) via the “Transmit Payload Data
Input Interface block.
Optionally accepts and insert overhead bits (into
the “outbound” DS3 data-stream) via the “Transmit
Overhead Input Interface block.
The Transmit DS3 Framer block will accept payload
data (from the Transmit Payload Data Input Inter-
face block) and overhead data (from the Transmit
Overhead Data Input Interface block) and will cre-
ate a DS3 data stream. If no overhead data is
inserted via the “Transmit Overhead Data Input
interface” block, then the “Transmit DS3 Framer”
block will insert its own values for the overhead bits.
The Transmit DS3 Framer block will transmit FEAC
(Far-End-Alarm & Control) messages to the remote
terminal equipment via an “on-chip” FEAC Trans-
mitter.
The Transmit DS3 Framer block will also transmit
PMDL (Path Maintenance Data Link) Messages to
the remote terminal equipment via an “on-chip”
LAPD Transmitter.
THE MICROPROCESSOR INTERFACE SECTION
The Microprocessor Interface Section allows a user (or
a local “housekeeping” processor) to do the following:
To configure the UNI/Framer IC into a wide variety
of operating modes; by writing data into any one of
a large number of “read/write” registers.
To monitor many aspects of the UNI/Framer’s perfor-
mance by reading data from any one of a large num-
ber of “read/write” and “read-only” registers.
To run in a “polling” or “interrupt-driven” environment.
The UNI/Framer IC contains an extensive interrupt
structure consisting of a wide range of interrupt
enable and interrupt status registers.
To command the UNI/Framer IC to transmit OAM
cells, FEAC messages and/or LAPD Messages
frames, upon software command.
To read in and process received OAM cells, FEAC
messages and/or Path Maintenance Data Link
Messages from the UNI/Framer IC.
The Microprocessor Interface allows the user to
interface the XRT72L73 DS3 UNI/Framer to either
an Intel type or Motorola type processor. Addition-
ally, the Microprocessor Interface can be configured
to operate over an 8-bit or 16-bit data bus.
The Microprocessor Interface section includes a
“Loss of Clock Signal” protection feature that auto-
matically completes (or terminates) a “Read/Write”
operation, should a “Loss of Clock Signal” event
occur.
PERFORMANCE MONITOR SECTION
The Performance Monitor Section of the XRT72L73
DS3 UNI/Framer consists of a large number of “Re-
set-upon-Read” and “Read-Only” registers that con-
tains cumulative and “one-second” statistics that re-
flect the performance/health of the UNI/Framer chip/
system. These cumulative and “one-second” statis-
tics are kept on the following parameters.
Number of Line Code Violation events detected by
the Receive DS3 Framer
Number of Framing Bit (F- and M-bit) errors
detected by the Receive DS3 Framer
Number of P-bit Errors detected by the Receive
DS3 Framer
Number of CP-bit Errors detected by the Receive
DS3 Framer.
Number of FEBE Events detected by the Receive
DS3 Framer
Cumulative number of BIP-8 errors, detected by the
Receive PLCP Processor
Number of PLCP framing errors, detected by the
Receive PLCP Processor
Cumulative sum of the FEBE value, in the incoming
G1 bytes (within each PLCP frame), received by
the Receive PLCP Processor
Number of Single-bit HEC byte Errors detected
Number of Multi-bit HEC byte Errors detected
Number of Received Idle Cells
Number of Received Valid (User and OAM) cells
discarded
Number of Discarded Cells
Number of Transmitted Idle Cells
Number of Transmitted Valid Cells
TEST AND DIAGNOSTIC SECTION
The Test and Diagnostic Section allows the user to
perform a series of tests in order to verify proper func-
tionality of the UNI/Framer chip and/or the user’s sys-
tem. The “Test and Diagnostic” section provides the
UNI IC with the following capabilities.
Allows the UNI/Framer to operate in the Line, Cell,
and PLCP Loop-back Modes.
FOR ATM UNI APPLICATIONS
Contains an internal Test Cell Generator and an
internal Test Cell Receiver. The Test Cell Generator
will generate Test Cells with “user-defined” header
byte patterns. The Test Cell Generator will also fill
the payload portion of these test cells with bytes
from an on-chip PRBS generator.
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| XRT72L74 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT7300IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7302 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L02M | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7300IV | 功能描述:外圍驅(qū)動器與原件 - PCI . . RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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