參數(shù)資料
型號(hào): XRT72L73
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 15/105頁
文件大?。?/td> 1307K
代理商: XRT72L73
á
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
15
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
Microprocessor Interface
AB3
AA4
AA1
AA2
Y1
Y2
Y3
W1
W2
A0
A1
A2
A3
A4
A5
A6
A7
A8
I
Address Bus Input (Microprocessor Interface):
These pins are used to select the on-chip UNI register and RAM space for READ/
WRITE operations with the “l(fā)ocal” microprocessor.
W3
V4
A9
A10
I
Channel Selection:
AC7
AD6
AE5
AF4
AC5
AD4
AE3
AF2
AB4
AC3
AD2
AB2
Y4
AA3
AC1
AE1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
I/O
Bi-Directional Data Bus (Microprocessor Interface Section):
These pins function as the Microprocessor Interface bi-directional data bus and is
intended to be interfaced to the “l(fā)ocal” microprocessor. This pin is inactive if the
Microprocessor Interface block is configured to operate over an 8 bit data bus.
AE2
ALE_AS
I
Address Latch Enable/Address Strobe:
This input is used to latch the address (present at the Microprocessor Interface
Address Bus, A[8:0]) into the UNI Microprocessor Interface circuitry and to indicate
the start of a READ/WRITE cycle. This input is active-"High" in the Intel Mode
(MOTO = “Low”) and active-”Low” in the Motorola Mode (MOTO = “High”).
AB1
CS
I
Chip Select Input:
This active-”Low” input signal selects the Microprocessor Interface Section of the
UNI/Framer and enables Read/Write operations between the “l(fā)ocal” microproces-
sor and the UNI/Framer on-chip registers and RAM locations.
AE4
Int
O
Interrupt Request Output:
This open-drain, active-”Low” output signal will be asserted when the UNI/Framer
is requesting interrupt service from the local microprocessor. This output pin
should typically be connected to the “Interrupt Request” input of the local micro-
processor.
A9
0
1
0
1
A10
0
0
1
1
Channel
0
1
2
Reserved
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