- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376461 > XRT72L73 (Exar Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT72L73 |
| 廠商： | Exar Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 25/105頁(yè) |
| 文件大?。?/td> | 1307K |
| 代理商： | XRT72L73 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)
á
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
25
B9
A9
D9
EncoDis_0
EncoDis_1
EncoDis_2
O
Encoder (B3ZS) Disable Output pin (intended to be connected to the
XRT73L03 E3/DS3/STS-1 LIU IC):
This output pin is intended to be connected to the EncoDis input pin of the
XRT73L03 LIU IC. The user can control the state of this output pin by writing a “0”
or “1” to Bit 3 (EncoDis) of the Line Interface Driver Register (Address = 0x72). If
the user commands this signal to toggle “High” then it will disable the B3ZS
encoder circuitry within the XRT73L03 IC. Conversely, if the user commands this
output signal to toggle “Low”, then the B3ZS Encoder circuitry, within the
XRT73L03 IC will be enabled.
Writing a “1” to Bit 3 of the Line Interface Driver Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause this
output pin to toggle “Low”.
N
OTES
:
1. The user is advised to disable the B3ZS encoder (within the XRT73L03 IC) if
the Tansmit and Receive DS3 Framers (within the UNI) are configured to
operate in the B3ZS line code.
2. If the designer is not using the XRT73L03 DS3/E3/STS-1 Line Transmitter
IC, then output pin can be used for other purposes.
External PLCP Frame Stuff Control:
This input allows the user to externally exercise or forego trailer nibble stuffing
opportunities by the Transmit PLCP Processor. PLCP trailer nibble stuff opportuni-
ties occur in periods of three PLCP frames (375μs). The first PLCP frame (first
within a “stuff opportunity” period) will have 13 trailer nibbles appended to it. The
second PLCP frame (second within a “stuff opportunity” period) will have 14 trailer
nibbles appended to it. The third PLCP frame (the location of the stuff opportunity)
will contain 13 trailer nibbles if the StuffCtl input is “Low” and 14 trailer nibbles is
the StuffCtl input is “High”.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
K3
K2
K1
StuffCtl_0
StuffCtl_1
StuffCtl_2
I
J3
J2
J1
TxOHInd/
TxPFrame_0
TxOHInd/
TxPFrame_1
TxOHInd/
TxPFrame_2
O
Transmit Overhead Data Indicator/Transmit PLCP Frame Boundary Indica-
tor—Output:
The exact functionality of this output pin depends upon whether the XRT72L71
Framer IC is operating in the Clear Channel or ATM Uni Mode.
Clear Channel Mode:
In the Clear Channel Mode, this pin serves as the transmit OH Indication for the
external interface. This pin is pulsed for one bit period of DS3 clock to indicate to
the external device that the transmit input interface is going to process OH data at
the rising edge of next clock. When the external interface samples TxOHInd as
“High” With the rising edge of DS3 Clk; it is expected NOT to provide useful pay-
load data bit on TxSer pin. Instead it can provide corresponding OH data bit on
TxSer input. However, in that case the user has to program a register bit to config-
ure XRT72L71 to accept the OH data from the TxSer input. Otherwise, the OH
data will be geaerated internally or be taken from the TxOH pin if TxOHIns is
“High”. This pin is pulsed "High" for one bit period prior to all DS3 OH bit positions.
ATM UNI Mode:
In ATM UNI mode of operation, this pin functions as Transmit PLCP Frame signal
which pulses "High" once for each outbound PLCP frame, when the last nibble is
being routed.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT72L74 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT7300IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7302 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L02M | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT72L73IB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7300IV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI . . RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。