參數(shù)資料
型號(hào)： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 66/105頁(yè)
文件大?。?/td> 1307K
代理商： XRT72L73
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER IC
REV. P1.0.1
á
PRELIMINARY
66
T
ABLE
28:
T
X
DS3 F-B
IT
M
ASK
4 R
EGISTER
R
EGISTER
27 T
X
DS3 F-B
IT
M
ASK
4 R
EGISTER
H
EX
A
DDRESS
: 0
X
1B
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
F-bit Mask (7)
R/W
0
The Transmit DS3 Framer block performs an XOR operation of the FBitMask
bits, with the corresponding “F” bits, within each outbound DS3 frame. FBit-
Mask(0) corresponds to first F-Bit (F1) is the DS3 frame, FBitMask (1) corre-
sponds to 2nd F-Bit (F0)in the DS3 frame,...FBitMask(27) corresponds to the
last F-Bit of the M-Frame.
N
OTES
:
1. Setting any of these bit-fields to “1” will cause an “erred” F-bit to be
transmitted onto the line.
2. For normal operation, set each of these bit-fields to “0”.
6
F-bit Mask (6)
R/W
0
5
F-bit Mask (5)
R/W
0
4
F-bit Mask (4)
R/W
0
3
F-bit Mask (3)
R/W
0
2
F-bit Mask (2
R/W
0
1
F-bit Mask (1)
R/W
0
0
F-bit Mask (0)
R/W
0
T
ABLE
29:
T
X
DS3 FEAC C
ONFIGURATION
AND
S
TATUS
R
EGISTER
R
EGISTER
28 T
X
DS3 FEAC C
ONFIGURATION
AND
S
TATUS
R
EGISTER
H
EX
A
DDRESS
: 0
X
1C
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-5
Unused
RO
0
4
Tx FEAC Interrupt Enable
R/W
0
0: Disables the “Transmit FEAC” Interrupt.
1: Enables the “Transmit FEAC” Interrupt.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to support
the “C-bit Parity” Framing format.
3
Tx FEAC Interrupt Status
RUR
0
0: Indicates that the “Transmit FEAC” Interrupt has not occurred since the
last read of this register.
1: Indicates that the “Transmit FEAC” Interrupt request has occurred since
the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to support
the “C-bit Parity” Framing format.
2
Tx FEAC Enable
R/W
0
0: The Transmit FEAC Processor is disabled, and cannot be commanded to
transmit a FEAC Message to the remote terminal equipment.
1: The Transmit FEAC Processor is enabled, and is able to be commanded
to transmit FEAC Messages to the remote terminal equipment.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to support
the “C-bit Parity” Framing format.
1
Tx FEAC Go
R/W
0
0 to 1 transition within this bit-field commands the Transmit FEAC Processor
to begin its transmission of the FEAC Message, which resides within the
“TxFEAC” Register.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to support
the “C-bit Parity” Framing format.
0
Tx FEAC Busy
RO
0
0: Indicates that the Transmit FEAC Processor is NOT currently transmitting
a FEAC Message to the remote terminal equipment
1: Data from FEAC register is currently being transmitted to the remote ter-
minal equipment.
N
OTE
:
This bit-field is only active if the XRT72L73 is configured to support
the “C-bit Parity” Framing format.
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