參數(shù)資料
型號(hào)： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 16/105頁(yè)
文件大?。?/td> 1307K
代理商： XRT72L73
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.1
á
PRELIMINARY
16
AF3
MOTO/Intel
I
Motorola/Intel Processor Interface Select Mode:
This input pin allows the user to configure the Microprocessor Interface to interface
with either a “Motorola-type” or “Intel-type” microprocessor/microcontroller. Tying this
input pin to VDD, configures the microprocessor interface to operate in the Motorola
mode (e.g., the UNI/Framer can be readily interfaced to a “Motorola type” local
microprocessor). Tying this input pin to GND configures the microprocessor inter-
face to operate in the Intel Mode (e.g., the UNI/Framer can be readily interfaced to
an “Intel type” local microprocessor).
Read Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this input will
function as the RD (READ STROBE) input signal from the local
μ
P
. Once this
active-”Low” signal is asserted, then the UNI/Framer will place the contents of the
addressed registers (within the UNI/Framer IC) on the Microprocessor Data Bus
(D[15:0]). When this signal is negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode):
If the microprocessor interface is operating in the Motorola mode, then this pin will
function as the active-”Low” Data Strobe signal.
READY or DTACK:
This active-”Low” output pin will function as the READY output, when the micropro-
cessor interface is running in the “Intel” Mode; and will function as the DTACK out-
put, when the microprocessor interface is running in the “Motorola” Mode.
Intel Mode—READY Output.
When the UNI negates this output pin (e.g., toggles it “Low”), it indicates (to the
μ
P) that the current READ or WRITE cycle is to be extended until this signal is
asserted (e.g., toggled “High”).
Motorola Mode:—DTACK (Data Transfer Acknowledge) Output.
The UNI Framer will assert this pin in order to inform the local microprocessor that
the present READ or WRITE cycle is nearly complete. If the UNI Framer requires
that the current READ or WRITE cycle be extended, then the UNI will delay its
assertion of this signal. The 68000 family of
μ
Ps requires this signal from its
peripheral devices, in order to quickly and properly complete a READ or WRITE
cycle.
Reset Input:
When this active-”Low” signal is asserted, the UNI Framer will be asynchronously
reset. Additionally, all outputs will be “tri-stated”, and all on-chip registers will be
reset to their default values.
Microprocessor Interface Block Data Bus Width Selector:
This input pin permits the user to configure the microprocessor interface of the
UNI/Framer, to operate over either an 8 or 16 bit wide bi-directional data bus. Tying
this pin to VDD configures the Microprocessor Interface Data Bus width to be 16
bits. Tying this pin to GND configures the Microprocessor Interface Data Bus width
to be 8 bits.
Write Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this active-”Low”
input pin functions as the WR (Write Strobe) input signal from the
μ
P Once this
active-”Low” signal is asserted, then the UNI will latch the contents of the
μ
P Data
Bus, into the addressed register (or RAM location) within the UNI/Framer IC.
R/W Input Pin (Motorola Mode):
When the Microprocessor Interface Section is operating in the “Motorola Mode”,
then this pin is functionally equivalent to the “R/W*” pin. In the Motorola Mode, a
“READ” operation occurs if this pin is at a logic “1”. Similarly, a WRITE operation
occurs if this pin is at a logic “0”.
AF1
RD_DS
I
AD1
RDY_DTCK
O
V2
Reset
I
AD5
Width16
I
AC2
WR_RW
I
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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