參數(shù)資料
型號(hào)： XRT72L73
廠商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 31/105頁(yè)
文件大?。?/td> 1307K
代理商： XRT72L73
á
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
31
Rx UTOPIA Interface
AD22
AF21
AE21
AC20
AF20
RxUAddr0
RxUAddr1
RxUAddr2
RxUAddr3
RxUAddr4
I
Receive UTOPIA Address Bus input:
These input pins function as the Receive UTOPIA Address bus inputs. These input
pins are only active when the UNI is operating in the Multi-PHY Mode. The Receive
UTOPIA Address Bus input is sampled on the rising edge of the RxUClk signal.
The contents of this address bus are compared with the value stored in the “Rx UT
Address Register (Address = 6Ch). If these two values match, then the UNI will
inform the ATM Layer Processor on whether or not it has any new ATM cells to be
read from the RxFIFO; by driving the RxUClav output to the appropriate level. If
these two address values do not match, then the UNI will not respond to the ATM
Layer Processor; and will keep its RxUClav output signal tri-stated.
N
OTE
:
The user should tie this pin to “GND”, whenever the XRT72L73 has been
configured to operate in the “Clear-Channel-Framer” Mode.
Receive UTOPIA—Cell Available:
The Receive UTOPIA Interface block will assert this output pin in order to indicate
that the Rx FIFO has some ATM cell data that needs to be read by the ATM Layer
Processor. The exact functionality of this pin depends upon whether the UNI is
operating in the “Octet Level” or “Cell Level” handshake mode.
Octet Level Handshaking Mode
When the Receive UTOPIA Interface block is operating in the “octet-level hand-
shaking” mode; this signal is asserted (toggles “High”) when at least one byte of
cell data exists within the RxFIFO (within the Receive UTOPIA Interface block).
This output pin will toggle “Low” if the RxFIFO is depleted of ATM cell data.
Cell Level Handshaking Mode
When the Receive UTOPIA Interface block is operating in the “cell-level handshak-
ing” mode; this signal is asserted if the RxFIFO contains at least one full cell of
data. This signal will toggle “Low” if the RxFIFO is depleted of data, or if it contains
less than one full cell of data.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this
signal will be tri-stated until the RxUClk cycle following the assertion of a valid
address on the Receive UTOPIA Address bus input pins (e.g., if the contents on
the Receive UTOPIA Address bus pins match that with the Receive UTOPIA
Address Register). Afterwards, this output pin will behave in accordance with the
cell-level handshake mode.
N
OTE
:
This output pin is only active if the XRT72L73 has been configured to oper-
ate in the “ATM UNI” Mode.
AE18
RxUClav
O
AD17
RxUClk
I
Receive UTOPIA Interface Clock Input:
The byte (or word) data, on the Receive UTOPIA Data bus is updated on the rising
edge of this signal. The Receive UTOPIA Interface can be clocked at rates up to 50
MHz.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer’” Mode.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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