參數(shù)資料
型號： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 24/105頁
文件大?。?/td> 1307K
代理商： XRT72L73
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.1
á
PRELIMINARY
24
M24
M25
M26
RxSerClk/
RxPOHClk_0
RxSerClk/
RxPOHClk_1
RxSerClk/
RxPOHClk_2
O
Clear Channel Mode Receive Clock Output Signal for Serial Data Interface/
Receive PLCP Frame Path Overhead (POH) Byte Serial Output Port—Output
Clock Signal:
The exact functionality of this output pin depends upon whether the XRT72L71
Framer IC is operating in the Clear Channel or ATM UNI Mode.
Clear Channel Mode - RxSerClk:
In clear channel mode, this pin can be used by the external interface to sample the
clear channel serial data stream on RxSer pin. The Receive Section of the
XRT72L71 will output all “inbound” DS3 data, via the “RxSerData” output pin,
upon the rising edge of this output pin. Hence, the user should be sampling the
data (on the “RxSerData” output pin) upon the rising edge of this clock.
ATM UNI MODE - RxPOHClk:
In the ATM UNI mode of operation, this pin serves as RxPOHClk.
This output clock pin, along with RxPOH, RxPOHframe pins comprise the
'Receive PLCP OH serial output' interface.
B3
C10
C19
RxPOS_0
RxPOS_1
RxPOS_2
I
Receive Positive Data Input:
The exact role of this input pin depends upon whether the UNI is operating in the
Unipolar or Bipolar Mode.
Unipolar Mode:
This input pin functions as the “Single-Rail” input for the “incoming” DS3 data
stream. The signal at this input pin will be sampled and latched (into the Receive
DS3 Framer) on the “user-selected” edge of the RxLineClk signal.
Bipolar Mode:
This input functions as one of the dual rail inputs for the incoming AMI/B3ZS
encoded DS3 data that has been received from an external Line Interface Unit
(LIU) IC. RxNEG functions as the other dual rail input for the UNI. When this input
pin is asserted, it means that the LIU has received a “positive polarity” pulse from
the line.
Tx PLCP Processor
G1
H3
H2
8KRef_0
8KRef_1
8KRef_2
I
8 kHz Reference Clock Input for the PLCP Processors:
The Transmit PLCP processor can be configured to synchronize its PLCP frame
processing to this clock signal. The Transmit PLCP Processor will also use this
signal to compute the trailer nibble stuff opportunities.
N
OTES
:
1. This input signal is active only if the user has configured the PLCP Pro-
cessors to use this signal as their “master clock” signal. The user can con-
figure the UNI to use this signal by setting TimRefSel[1,0] (within the UNI
Operating Mode Register) to 01.
2. The user should tie this pin to “GND” whenever the XRT72L73 has been
configured to operate in the “Clear-Channel-Framer” Mode.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT72L73IB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
XRT72L74IB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
XRT7300 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7300ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT7300IV 功能描述:外圍驅(qū)動器與原件 - PCI . . RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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