參數(shù)資料
型號(hào)： XRT72L73
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 30/105頁(yè)
文件大?。?/td> 1307K
代理商： XRT72L73
XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.1
á
PRELIMINARY
30
AD10
TxUClk
I
Transmit UTOPIA Interface Clock:
The Transmit UTOPIA Interface clock is used to latch the data on the Transmit
UTOPIA Data bus, into the Transmit UTOPIA Interface block. This clock signal is
also used as the timing source for circuitry used to process the ATM cell data into
and through the TxFIFO.
During Multi-PHY operation, the data on the Transmit UTOPIA Address bus pins is
sampled on the rising edge of TxUClk.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
Transmit UTOPIA Data Bus Input:
These pins comprise the Transmit UTOPIA Data Bus input pins. When the ATM
Layer Processor wishes to transmit ATM cell data through the XRT72L73 DS3
UNI, it must place this data on these pins. The data, on the Transmit UTOPIA Data
Bus is latched into the Transmit UTOPIA Interface block on the rising edge of TxU-
Clk.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
AF16
AE16
AD16
AF15
AE15
AD15
AC14
AF14
AD14
AF13
AE13
AD13
AC12
AF12
AE12
AD12
TxUData0
TxUData1
TxUData2
TxUData3
TxUData4
TxUData5
TxUData6
TxUData7
TxUData8
TxUData9
TxUData10
TxUData11
TxUData12
TxUData13
TxUData14
TxUData15
I
AE14
TxUPrty
I
Transmit UTOPIA Data Bus—Parity Input:
The ATM Layer processor will apply the parity value of the byte or word which is
being applied to the Transmit UTOPIA Data Bus (e.g., TxUData[7:0] or TxU-
Data[15:0]) inputs of the UNI, respectively. Note: this parity value should be com-
puted based upon the odd-parity of the data applied at the Transmit UTOPIA Data
Bus. The Transmit UTOPIA Interface block (within the UNI) will independently com-
pute an odd-parity value of each byte (or word) that it receives from the ATM Layer
processor and will compare it with the logic level of this input pin.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
Transmitter—Start of Cell (SoC) Indicator Input:
This input pin is driven by the ATM Layer processor and is used to indicate the
start of an ATM cell that is being transmitted from the ATM layer processor. This
input pin must be pulsed “High” when the first byte (or word) of a new cell is
present on the Transmit UTOPIA Data Bus. This input pin must remain “Low” at all
other times.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L73 has
been configured to operate in the “Clear-Channel-Framer” Mode.
AC9
TxUSoC
I
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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