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XRT72L73
THREE CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
PRELIMINARY
REV. P1.0.1
23
J25
J26
J23
RxLOS_0
RxLOS_1
RxLOS_2
O
Receive DS3 Framer—Loss of Signal Output Indicator:
This pin is asserted when the Receive DS3 Framer encounters 180 consecutive
0’s via the RxPOS and RxNEG pins. This pin will be negated once the Receive DS3
Framer has detected at least 60 “1s” out of 180 consecutive bits.
B4
C12
C17
RxNEG_0
RxNEG_1
RxNEG_2
I
Receive Negative Data Input:
The exact role of this input pin depends upon whether the UNI is operating in the
Unipolar or Bipolar Mode.
Unipolar Mode:
This input pin is inactive, and should be pulled (“Low” or "High") when the UNI is
operating in the Unipolar Mode.
Bipolar Mode:
This input pin functions as one of the dual rail inputs for the incoming AMI/B3ZS
encoded DS3 data that has been received from an external Line Interface Unit
(LIU) IC. RxPOS functions as the other dual rail input for the UNI. When this input
pin is asserted, it means that the LIU has received a “negative polarity” pulse from
the line.
B26
A25
B25
RxOH_0
RxOH_1
RxOH_2
O
Receive Overhead Output Port:
All overhead bits, which are received via the "Receive Section" of the Framer IC;
will be output via this output pin, upon the rising edge of RxOHClk.
B23
A23
C22
RxOHClk_0
RxOHClk_1
RxOHClk_2
O
Receive Overhead Output Clock Signal:
This pin serves as the clock signal for external device to sample the Overhead
data on the RxOH pin. The external interface should use the rising edge of this
clock to sample the OH data on RxOH pin.
D21
C20
B20
RxOHFrame_0
RxOHFrame_1
RxOHFrame_2
O
Receive Overhead Frame Boundary Indicator:
This pin is pulsed “High” for one RxOHClk period whenever the first 'X' bit is output
on RxOH pin. If external device samples this pin “High” on the rising edge of RxO-
HClk, the data on RxOH is 'X' bit (first OH bit in the received DS3 frame).
H25
H26
G24
RxOOF_0
RxOOF_1
RxOOF_2
O
Receiver DS3 Framer—“Out of Frame” Indicator:
The Receive DS3 Framerblock will assert this output signal (e.g., pull it “High”)
whenever it has declared an “Out of Frame” (OOF) condition with the incoming
DS3 frames. This signal is negated when the framer correctly locates the F- and
M-bits and regains synchronization with the DS3 frame.
R26
P24
P25
RxSerData/
RxPOH_0
RxSerData/
RxPOH_1
RxSerData/
RxPOH_2
O
Receive Serial Output/Receive PLCP Frame Path Overhead (POH) Byte
Serial Output Port—Output Pin:
The exact functionality of this output pin depends upon whether the XRT72L71
Framer IC is operating in the Clear Channel or ATM UNI Mode.
Clear Channel Mode:
In clear channel mode, all DS3 data which is received by XRT72L71 will be output
as a serial data stream via this pin. The XRT72L71 will output data (via this pin)
upon the falling edge of “RxSerClk”. As a consequence, this data should be sam-
pled with the rising edge of RxSerClk.
ATM UNI Mode:
This output pin, along with RxPOHClk, RxPOHFrame, and RxPOHIns pins com-
prise the “Receive PLCP Frame POH Byte” serial output port. For each PLCP
frame that is received by the Receive PLCP Processor, this serial output port will
output the contents of all 12 POH (Path Overhead) bytes. The data that is output
via this pin, is updated on the rising edge of the RxPOHClk output clock signal.
The RxPOHFrame pin will pulse “High” when the first bit of the Z6 byte is being
output on this output pin.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION