參數(shù)資料
型號： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù)： 74/82頁
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
74
μ
PD46128512-X
9. Mode Register Setting Timing
Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing + CLK fixed LOW/HIGH)
H
/LB, /UB (Input)
/WE (Input)
/CE1 (Input)
Address (Input)
/OE (Input)
DQ (Input/Output)
t
RC
t
WC
t
WC
7FFFFFH
t
WP
t
WR
t
WP
t
WR
t
DW
t
DH
t
DW
t
DH
7FFFFFH
7FFFFFH
7FFFFFH
Code1
Code2
High-Z
High-Z
High-Z
7FFFFFH
t
WC
t
WP
t
WR
t
DW
t
DH
t
WC
t
WP
t
WR
t
DW
t
DH
High-Z
t
RC
Don't care
High-Z
t
CE
t
OE
RDa
t
CE
t
OE
RDb
High-Z
High-Z
t
OHZ
t
CHZ
t
OHZ
t
CHZ
Don't care
Don't care
CLK (Input)
L
Remarks 1.
For the data of Code1 and Code2, refer to
Table 5-1. Mode Register Definition (4th Bus Cycle)
and
Table 5-2. Mode Register Definition (5th Bus Cycle)
.
2.
RDa and RDb are the output data.
3.
/ADV fixed LOW or toggle HIGH
→
LOW
→
HIGH.
Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + Toggle CLK)
/LB, /UB (Input)
/WE (Input)
/CE1 (Input)
Address (Input)
/OE (Input)
DQ (Input/Output)
t
RC
t
WC
t
WC
7FFFFFH
t
WP
t
WR
t
WP
t
WR
t
DW
t
DH
t
DW
t
DH
7FFFFFH
7FFFFFH
7FFFFFH
High-Z
High-Z
High-Z
7FFFFFH
t
WC
t
WP
t
WR
t
DW
t
DH
t
WC
t
WP
t
WR
t
DW
t
DH
High-Z
t
RC
High-Z
t
CE
t
OE
RDa
t
CE
t
OE
RDb
High-Z
High-Z
t
OHZ
t
CHZ
t
OHZ
t
CHZ
CLK (Input)
Code1
Code2
Don't care
Don't care
Don't care
Remarks 1.
For the data of Code1 and Code2, refer to
Table 5-1. Mode Register Definition (4th Bus Cycle)
and
Table 5-2. Mode Register Definition (5th Bus Cycle)
.
2.
RDa and RDb are the output data.
3.
/ADV fixed LOW or toggle HIGH
→
LOW
→
HIGH.
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