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參數(shù)資料
| 型號： | UPD46128512F9-CR2 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍 |
| 文件頁數(shù)： | 22/82頁 |
| 文件大小： | 817K |
| 代理商： | UPD46128512F9-CR2 |
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Preliminary Data Sheet M17507EJ2V0DS
22
μ
PD46128512-X
4.10 /WAIT
4.10.1
Feature of /WAIT Output
The /WAIT output signal indicates the internal status, busy (LOW) or ready (HIGH), during the burst read and burst
write operation.
The /WAIT output state changes depend on the /CE1 and /ADV condition. When /CE1 held entire LOW, the /WAIT
output corresponds with /ADV state and turns to LOW by /ADV assertion. The /WAIT output stays high impedance at
standby mode (/CE1 = HIGH) and turns to LOW at active mode brought by /CE1 assertion.
The /WAIT output will be asserted to LOW after specific time duration triggered by falling edge of /CE1, or falling edge
of /ADV when /CE1 held entire LOW. When the /WAIT output LOW, it indicates the output data is not valid at the next
clock cycle.
The /WAIT output asserts HIGH one clock cycle before the valid data output.
The /WAIT output retains the same state as of the clock cycle right before being suspended with /OE brought to HIGH.
Figure 4-7. Burst Read /WAIT Output (/CE1 = HIGH
T0
→
LOW)
T1
T3
T2
T4
T5
CLK (Input)
/ADV (Input)
A0 to A22 (Input)
/CE1 (Input)
/WE (Input)
DQ0 to DQ15 (Output)
/WAIT (Output)
Add
H
RL = 5
High-Z
Q0
High-Z
t
CEWA
t
CLWA
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