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參數(shù)資料
| 型號： | UPD46128512F9-CR2 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內存800萬字由16位溫度范圍 |
| 文件頁數(shù)： | 31/82頁 |
| 文件大?。?/td> | 817K |
| 代理商： | UPD46128512F9-CR2 |
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Preliminary Data Sheet M17507EJ2V0DS
31
μ
PD46128512-X
5.9 /WE Control
Sets the /WE timing in burst write operation and burst write suspend / resume available or not. Setting DQ4 to 0 at the
5th bus cycle sets /WE single clock control, and burst write suspend / resume are not supported. In single clock control,
/WE is available at the 1st clock edge of /ADV = LOW; setting DQ4 to 1 at the 5th bus cycle sets /WE level control, and
burst write suspend / resume are supported. In level control, /WE is sure to transfer LOW to HIGH after latching last
write data in burst write operation.
Refer to
Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control), Figure 8-11. Synchronous Burst Write
Suspend Timing Chart
.
5.10 Reset to Page Mode
Sets the Reset function from synchronous burst mode to asynchronous page mode. Setting DQ7 to 0 at the 5th bus
cycle sets reset available from synchronous burst mode to asynchronous page mode. Setting DQ7 to 1 at the 5th bus
cycle sets reset unavailable.
5.11 Reserved Bits
Reserved bits must be 1 because reserved bits are used for internal test mode entry. Be sure to set DQ15 to DQ7 to 1
at the 4th and DQ15 to DQ8 and DQ6 and DQ5 at the 5th bus cycles.
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