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參數(shù)資料
| 型號(hào)： | UPD46128512F9-CR2 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動(dòng)指明內(nèi)存800萬(wàn)字由16位溫度范圍 |
| 文件頁(yè)數(shù)： | 27/82頁(yè) |
| 文件大小： | 817K |
| 代理商： | UPD46128512F9-CR2 |
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Preliminary Data Sheet M17507EJ2V0DS
27
μ
PD46128512-X
4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode
Even during the burst operation mode, the
μ
PD46128512-X has the reset feature of changing synchronous burst
mode to asynchronous page mode.
This reset is achieved by toggling CE2 signal HIGH
→
LOW
→
HIGH.
This reset to asynchronous page mode can be enable / disable with mode register setting.
Since the CE2 signal originally controls partial refresh function, the partial refresh operation can also be performed
during the reset operation according to the density specified in the mode register. Please refer to the timing diagram and
requirement below. Note that the timing requirement differs with the partial refresh density.
In case when the reset to asynchronous page mode is disabled in the mode register, only the partial refresh operation
can be performed with CE2 signal toggling. Refer to
Figure 2-1. Standby Mode State Machine
.
Figure 4-11. Reset Entry Timing Chart to Asynchronous Page Mode
/CE1 (Input)
t
CHML
t
MHCL
CE2 (Input)
t
CE2S
t
CES
CLK (Input)
t
RST
Reset to Page Standby Mode2
Asynchronous Page Operation
Synchronous Burst Operation
Parameter
Symbol
MIN.
MAX.
Unit
Note
Reset to asynchronous page and standby mode2 entry
t
CHML
0
ns
/CE1 HIGH to CE2 LOW
Reset to asynchronous page and standby mode2 to normal operation
t
MHCL
30
ns
1
CE2 HIGH to /CE1 LOW
300
μ
s
2
/CE1 = HIGH setup time to CLK
t
CES
5
ns
CE2 = LOW hold time to CLK
t
CE2S
1
ns
Reset time to asynchronous page mode
t
RST
70
ns
Notes 1.
In case the density for partial refresh are 32M bits / 16M bits / 8M bits in standby mode2
2.
In case the density for partial refresh is 0M bits in standby mode2
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