參數(shù)資料
型號(hào)： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存800萬(wàn)字由16位溫度范圍
文件頁(yè)數(shù)： 37/82頁(yè)
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
37
μ
PD46128512-X
Asynchronous Write Cycle
Parameter
Symbol
-E9X, -E11X
-E10X, -E12X
Unit
Note
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
ns
/CE1 to end of write
t
CW
50
60
ns
Address valid to end of write
t
AW
55
60
ns
/LB, /UB to end of write
t
BW
50
60
ns
Write pulse width
t
WP
50
55
ns
Write recovery time
t
WR
0
0
ns
Write recovery time (/WE = HIGH
→ /
CE1 = HIGH)
t
WHCH
0
10,000
0
10,000
ns
/CE1 pulse width
t
CP
10
10
ns
/LB, /UB HIGH pulse width
t
BP
10
10
ns
/WE HIGH pulse width
t
WHP
10
10
ns
/WE HIGH pulse width (/CE1 = LOW)
t
WHP1
10
10,000
10
10,000
ns
Address setup time
t
AS
0
0
ns
/CE1 HIGH to address hold
t
CHAH
0
0
ns
1
/LB, /UB HIGH to address hold
t
BHAH
0
0
ns
/LB, /UB byte mask setup time
t
BS
0
0
ns
/LB, /UB byte mask hold time
t
BH
0
0
ns
/LB, /UB byte mask over wrap time
t
BWO
30
30
ns
Data valid to end of write
t
DW
25
25
ns
Data hold time
t
DH
0
0
ns
Address set to /ADV HIGH
t
ASV
7
7
ns
/ADV HIGH to address hold
t
AH
3
3
ns
/ADV LOW pulse width
t
VPL
7
7
ns
/OE HIGH to /WE set
t
OES
10
10,000
10
10,000
ns
2
/WE HIGH to /OE set
t
OEH
10
10,000
10
10,000
ns
Notes 1.
When t
AS
≥
| t
CHAH
| and t
CP
≥
18 ns, t
CHAH
(MIN.) is –15 ns.
t
CHAH
t
ASO
/CE1 (Input)
Address (Input)
/OE (Input)
2.
t
OES
and t
OEH
(MAX.) are applied while /CE1 is being hold at LOW.
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