參數(shù)資料
型號: UPD46128512F9-CR2
廠商: NEC Corp.
英文描述: 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述: 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù): 72/82頁
文件大小: 817K
代理商: UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
72
μ
PD46128512-X
Figure 8-15. Synchronous Burst Write – Burst Read Cycle Timing Chart (/CE1 Control)
CLK (Input)
/ADV (Input)
Address (Input)
/CE1 (Input)
/WAIT (Output)
/OE (Input)
DQ (Input/Output)
/LB, /UB (Input)
/WE (Input)
t
CH
t
CL
Q0
t
ACS
t
BACC
t
BDH
t
WDH
t
WDS
t
BC
t
OC
t
LUH
t
CLWA
t
CSV
t
CES
t
CEH
t
ACH
t
CHV
t
AH
RL = 5
t
CHV
t
WEH
t
CYCLE
D
BL
High-Z
Valid
t
VPL
t
WRB
t
CLZ
t
CEWA
High-Z
t
CWHZ
t
CP
t
BLZ
t
OLZ
Remarks 1.
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
D
BL
means the latest data input of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
t
OC
and t
BC
are defined from CLK rising edge of RL
1 to /OE = LOW, /LB and /UB = LOW.
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