參數(shù)資料
型號(hào)： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù)： 28/82頁
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
28
μ
PD46128512-X
5. Mode Register Settings
The
μ
PD46128512-X has several modes, Page Read mode, Burst Read mode, Burst write mode, Single Write mode,
Asynchronous Write mode, Deep Power Down mode, Partial Refresh mode.
Mode Resister setting defines Partial Refresh Density, Burst Length, Latency, Burst Sequence, Write mode (Burst or
Single), Valid Clock Edge, Support burst write suspend/resume or not .
The several modes can be set using mode register. Since the initial value of the mode register at power application is
undefined, be sure to set the mode register after initialization at power application.
5.1 Mode Register Setting Method
To set each mode, write any data twice, write specific data twice, read any address in succession after the highest
address (7FFFFFH) is read (6 cycles in total).
Cycle
Operation
Address
Data
1st cycle
Read
7FFFFFH
Read Data (RDa)
2nd cycle
Write
7FFFFFH
RDa
Note
or Don’t care
3rd cycle
Write
7FFFFFH
RDa
Note
or Don’t care
4th cycle
Write
7FFFFFH
Code 1
5th cycle
Write
7FFFFFH
Code 2
6th cycle
Read
Don’t care
Read Data (RDb)
Note
In order to hold
the highest address (7FFFFFH) cell data during mode register setting, be sure to set the same
data with 1st cycle read data in the 2nd and 3rd cycle (write cycle).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to
Figure 9-1. Mode Register Setting Timing Chart (Asynchronous
Timing + CLK fixed LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle
CLK), Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing), Figure 9-4. Mode Register Setting
Flow Chart.
Table 5-1, Table 5-2
shows the commands and command sequences.
5.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CE1 and /OE, toggle /CE1 at
every cycle during entry (one read cycle, four write cycles and one read cycle), and toggle /OE like /CE1 at the first and
the 6th read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register is not performed correctly.
Cancellation of the mode register setting must be performed before the write in the 3rd bus cycle is determined.
Cancellation in the 4th bus cycle or later should not be performed. If performed, data and previous register setting are
not guaranteed, so the mode register must be re-setup after the 6th bus cycle is complete.
When the highest address (7FFFFFH) is read consecutively two or more times, the mode register setting entries are
not performed correctly. Mode setting is available after power application and read or write operation other than the
highest address (7FFFFFH) are performed.
Once the several modes have been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined except page mode (M = 1) if the
power is turned off, so set the mode register again after power application.
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