參數(shù)資料
型號： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù)： 29/82頁
文件大小： 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
29
μ
PD46128512-X
For the timing chart and flow chart, refer
Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing
+ CLK fixed LOW/HIGH)
,
Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle CLK)
,
Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing)
,
Figure 9-4. Mode Register Setting Flow
Chart
.
Table 5-1. Mode Register Definition (4th Bus Cycle)
Data Code
Symbol
Function
Value
Description
DQ1, DQ0
PS
Partial Refresh Density
00
32M bit
01
16M bit
10
8M bit
11
0M bit
DQ4 to DQ2
BL
Burst Length
010
8 word
011
16 word
111
Continuous
Others
Reserved
DQ5
M
Function Mode
0
Burst
1
Page
DQ6
VE
Valid Clock Edge
0
Falling Edge
1
Rising Edge
DQ15 to DQ7
111111111
Reserved (All “1” are necessary)
Table 5-2. Mode Register Definition (5th Bus Cycle)
Data Code
Symbol
Function
Value
Description
DQ2 to DQ0
RL
Read Latency
010
5 (Write Latency = 4)
(Write Latency)
011
6 (5)
100
7 (6)
101
8 (7)
110
9 (8)
111
10 (9)
Others
Reserved
DQ3
SW
Single Write
0
Burst Read & Burst Write
1
Burst Read & Single Write
DQ4
WC
/WE Control
0
Single clock control without suspend
1
Level control with suspend
DQ6, DQ5
11
Reserved (All “1” are necessary)
DQ7
RP
Reset to Page mode
0
Reset available to Page mode
1
Reset not available to Page mode
DQ15 to DQ8
11111111
Reserved (All “1” are necessary)
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