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參數(shù)資料
| 型號： | UPD46128953-E15X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內存分詞由32位地址/數(shù)據(jù)復用溫度范圍 |
| 文件頁數(shù)： | 1/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-E15X |
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Document No. M17506EJ1V1DS00 (1st edition)
Date Published September 2005 CP (K)
Printed in Japan
MOS INTEGRATED CIRCUIT
μ
PD46128953-X
128M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 32-BIT
ADDRESS / DATA MULTIPLEXED
EXTENDED TEMPERATURE OPERATION
PRELIMINARY DATA SHEET
2005
Description
The
μ
PD46128953-X is a high speed, low power, 134,217,728 bits (4,194,304 words by 32 bits) CMOS Mobile
Specified RAM featuring synchronous burst read and synchronous burst write function.
The
μ
PD46128953-X realizes high performance with the SDR interface, command and data inputs / outputs are
synchronized the rising edge of clock.
The
μ
PD46128953-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
4,194,304 words by 32 bits organization
Low voltage operation: 1.7 to 2.0 V (1.85
±
0.15 V)
Operating ambient temperature: T
A
=
25 to
+
85 °C
Synchronous burst mode
Burst length
: 8 double words (Wrap)
Burst sequence
: Linear burst
Maximum clock frequency : 83 / 66 MHz
SDR (Single Data Rate) Architecture
One data transfers per one clock cycle
All inputs/outputs are synchronized with the positive edge of the clock
Write data mask (DM) for write operation
Output Enable: /OE pin
Chip Enable input: /CE1 pin
Standby Mode input: CE2 pin
Standby Mode 1: Normal standby (Memory cell data hold valid)
Standby Mode 2: Density of memory cell data hold is variable
μ
PD46128953
Clock
Operating
Operating
Supply current
frequency
supply
ambient
At operating mA
At standby
μ
A
MHz
voltage
temperature
(MAX.)
(MAX.)
(MAX.)
V
°C
-E12X
Note
83
1.7 to 2.0
25 to
+
85
60
T.B.D.
-E15X
66
55
Note
Under consideration
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