參數(shù)資料
型號(hào): UPD46128953-E15X
廠商: NEC Corp.
英文描述: 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述: 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁(yè)數(shù): 47/60頁(yè)
文件大?。?/td> 468K
代理商: UPD46128953-E15X
Preliminary Data Sheet M17506EJ1V1DS
47
μ
PD46128953-X
Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 Controlled)
T0
T1
T2
T3
T4
T5
T6
T7
T0
T1
T2
T3
T4
T5
T6
T7
Q0
Q1
Q2
Q0
Q0
Q1
Q2
Q0
Add
Add
t
CLK
t
CH
t
CL
High-Z
High-Z
t
CSV
t
CHV
t
AH
t
CES
t
OLZ
t
CEWA
t
WES
t
WEH
t
WES
t
WEH
t
VPL
t
CEWA
t
CWHZ
t
OES
t
OEH
t
AOS
Read Latency = 6
t
OLZ
t
OES
t
OEH
t
CHV
t
CSV
t
CHV
t
CHV
t
CES
t
CEH
t
CES
t
AH
t
VPL
t
CEH
t
OES
t
OEH
t
AC
t
OH
t
CLWA
t
CLWA
High-Z
t
ACS
t
ACH
t
AOS
High-Z
t
ACS
t
ACH
High-Z
High-Z
t
AC
t
AC
t
HZ
Read Latency = 6
High-Z
High-Z
CLK (Input)
/ADV (Input)
/CE1 (Input)
/WAIT (Output)
/OE (Input)
A/DQ0 to A/DQ21 (Input/Output)
/WE (Input)
DQ22 to DQ31 (Output)
Note
Burst Read Termination is available after the first read data output.
Figure 7-5 is the minimum cycle at Burst Read Termination to next operation.
Remark
The above timing chart assumes read latency is set 6.
相關(guān)PDF資料
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UPD46128953-X 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
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