參數(shù)資料
型號(hào)： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù)： 30/82頁
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
30
μ
PD46128512-X
5.3 Partial Refresh Density
The density for performing refresh in power down mode can be set with mode register. Setting DQ1 and DQ0 to 00 at
the 4th bus cycle sets a partial refresh density of 32 M-bit hold; setting DQ1 and DQ0 to 01 at the 4th bus cycle sets a
partial refresh density of 16 M-bit hold; setting DQ1 and DQ0 to 10 at the 4th bus cycle sets a partial refresh density of 8
M-bit hold; and setting DQ1 and DQ0 to 11 at the 4th bus cycle sets a partial refresh density of 0 (no hold).
Since the Partial Refresh mode is not entered unless CE2 = LOW, when partial refresh is not used, it is not necessary
to set the mode register.
5.4 Burst Length
Sets the burst length in the burst mode. Setting DQ4 to DQ2 to 010 at the 4th bus sets 8word of burst length; setting
DQ4 to DQ2 to 011 at the 4th bus cycle sets 16word of burst length; setting DQ4 to DQ2 to 111 at the 4th bus cycle sets
continuous of burst length
5.5 Function Mode
Select function mode. Setting DQ5 to 0 at the 4th bus sets a function mode of burst and setting DQ5 to 1 at the 4th
bus sets a function mode of page. After power application, page mode is set as an initial state.
5.6 Valid Clock Edge
Select valid clock edge (Rising edge or Falling edge) in the burst mode. Setting DQ6 to 0 at the 4th bus cycle sets
clock falling edge; setting DQ6 to 1 at the 4th bus cycle sets clock rising edge.
5.7 Read Latency (Write Latency)
Sets the number of clock cycles (latency) between the address input and the output of the first data in the burst read
mode, the address input and the write data input in the burst write mode. Setting DQ2 to DQ0 to 010 at the 5th bus cycle
sets read latency of 5; setting DQ2 to DQ0 to 011 at the 5th bus sets read latency of 6; setting DQ2 to DQ0 to 100 at the
5th bus sets read latency of 7; setting DQ2 to DQ0 to 101 at the 5th bus sets read latency of 8; setting DQ2 to DQ0 to
110 at the 5th bus sets read latency of 9; setting DQ2 to DQ0 to 111 at the 5th bus sets read latency of 10. Once specific
RL is set through Mode Register Setting sequence, write latency, that is the number of clock cycles between address
input and first write data input, is automatically set to RL
1.
For the latency count, refer to
Figure 4-1. Latency Definition
5.8 Single Write
Sets the write mode. Setting DQ3 to 0 at the 5th bus cycle sets burst write mode; setting DQ3 to 1 at the 5th bus cycle
sets single write mode.
相關(guān)PDF資料
PDF描述
UPD46128953-E15X 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
UPD46128953-X 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
UPD4616112F9-B95LX-BC2 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
UPD4616112F9-B85LX-BC2 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
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