參數(shù)資料
型號： UPD46128512F9-CR2
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍
文件頁數(shù)： 25/82頁
文件大?。?/td> 817K
代理商： UPD46128512F9-CR2
Preliminary Data Sheet M17507EJ2V0DS
25
μ
PD46128512-X
4.10.2
Dummy Wait Cycles at Continuous Burst Operation
In continuous burst operation, dummy wait cycles may be needed when a burst sequence crosses the first 16-word
boundary. Whether dummy wait cycles is needed or not depends on start address and the number of dummy wait cycles
depends on Read Latency (See
Table 4-1. Burst Sequence
and
4-2. Dummy Wait Cycles and Read Latency
).
During the dummy cycle period, /WAIT output LOW.
Table 4-1. Burst Sequence
Start
Burst length = 8
Burst length = 16
Continuous
Address
Linear
Linear
Linear
xx00 H
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-…
xx01 H
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-…
xx02 H
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-…
xx03 H
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-…
xx04 H
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-…
xx05 H
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-…
xx06 H
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-…
xx07 H
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-…
xx08 H
8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-…
xx09 H
9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8
9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-…
xx0A H
10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9
10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-25-…
xx0B H
11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10
11-12-13-14-15-
W
-16-17-18-19-20-21-22-23-24-25-…
xx0C H
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
12-13-14-15-
W
-
W
-16-17-18-19-20-21-22-23-24-25-…
xx0D H
13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
13-14-15-
W
-
W
-
W
-16-17-18-19-20-21-22-23-24-25-…
xx0E H
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-
W
-
W
-
W
-
W
-16-17-18-19-20-21-22-23-24-25-…
xx0F H
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-
W
-
W
-
W
-
W
-
W
-16-17-18-19-20-21-22-23-24-25-…
xx10 H
…
16-17-18-19-20-21-22-23-24-25-26-…
xx11 H
17-18-19-20-21-22-23-24-25-26-27-…
…
…
…
…
xxnB H
-xxnB -xxnC-xxnD-xxnE-xxnF-
W
-xx(n+1)0-xx(n+1)1-…
xxnC H
-xxnC-xxnD-xxnE-xxnF-
W
-
W
-xx(n+1)0-xx(n+1)1-…
xxnD H
-xxnD-xxnE-xxnF-
W
-
W
-
W
-xx(n+1)0-xx(n+1)1-…
xxnE H
-xxnE-xxnF-
W
-
W
-
W
-
W
-xx(n+1)0-xx(n+1)1-xx(n+1)2-…
xxnF H
-xxnF-
W
-
W
-
W
-
W
-
W
-xx(n+1)0-xx(n+1)1-xx(n+1)2-…
…
…
…
…
Remarks 1.
The above table assumes Read Latency is set 5.
W
shows Dummy Wait Cycles.
2.
Address is in HEX.
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