參數(shù)資料
型號: TECO3264
廠商: Lineage Power
英文描述: 32-Channel Echo Canceller(32通道回波清除器)
中文描述: 32通道回聲消除器(32通道回波清除器)
文件頁數(shù): 79/128頁
文件大?。?/td> 2328K
代理商: TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
79
Lucent Technologies Inc.
Register Architecture
(continued)
Page 0 Read/Write Registers 000
07FE
(continued)
SRAM Control Register
Table 45. SRAM Control Register (034) [01]
Y Port Control 1 Register
Table 46. Y Port Control 1 Register (035) [02]
Bit
0
Symbol
WEMODE
Parameter Name and Description
Write Enable Mode.
Write enable mode for external SRAM.
Set to 1.
Reserved.
Set to 0.
7—1
Bit
0
Symbol
YRCE
Parameter Name and Description
Y Receive Clock Edge.
Determines the edge of the clock that will be used to sample the
YPCM data input.
0 = Negative-going/falling edge sampling [recommended value].
1 = Positive-going/rising edge sampling.
Y Receive Bit Offset [3:0].
These 4 bits provide a fixed offset, relative to the frame-syn-
chronization pulse (SYNC), for the first bit received in each time slot. The offset is the
number of data periods by which reception of the first bit on [Y] is delayed. All subse-
quent receptions of the first bit also follow this offset. One data period (1 bit) is equal to 4
cycles of CK8M for CMS = 1, and 2 cycles of CK8M for CMS = 0. Received data is sam-
pled in the middle of the data bit.
Y Parity[2:0].
Selects various parity options that may be applied to the Y input.
4—1
YRBOFF[3:0]
7—5
YPY[2:0]
YPY0: 1 = enable parity checking; 0 = disable.
YPY1: 1 = even parity; 0 = odd parity.
YPY2: 1 = bit 8; 0 = bit 15.
Recommended value = 000.
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