參數(shù)資料
型號: TECO3264
廠商: Lineage Power
英文描述: 32-Channel Echo Canceller(32通道回波清除器)
中文描述: 32通道回聲消除器(32通道回波清除器)
文件頁數(shù): 38/128頁
文件大?。?/td> 2328K
代理商: TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
38
Lucent Technologies Inc.
Parameters
(continued)
PCM Transmission Parameters
(continued)
* See note in Bit Offset Operation section on page 22.
Table 14. Transmission Parameters
(continued)
Symbol
Description
Memory Map
Starting Address (Hex)
XDLY[4:0]
X
C delay. Provides up to one complete frame delay.
XDLY X
C direction bulk time-slot delay.
Y
E delay. Provides up to one complete frame delay.
YDLY Y
E direction bulk time-slot delay.
Exercise parity error.
0x30
YDLY[4:0]
0x31
EX
0x32
XCOMP
X input companded/linear select.
0x32
EET
Enable edge transfer bit for sync sampling.
Frame edge. This bit allows the flexibility to sample the SYNC pulse on
either a rising or a falling edge of CK8M.
0 = SYNC is sampled on the falling edge of CK8M.
1 = SYNC is sampled on the rising edge of CK8M.
Write enable mode for external SRAM.
Y receive clock edge.
0 = sample receive data on the falling edge of CK8M*.
1 = sample receive data on the rising edge of CK8M*.
YRBOFF[3:0] Y receive bit offset. These 4 bits provide a fixed offset, relative to the
frame-synchronization pulse (SYNC), for the first bit received in each
time slot. The offset is the number of data periods by which reception
of the first bit on [Y] is delayed. All subsequent receptions of the first bit
also follow this offset. One data period (1 bit) equals to 4 cycles of
CK8M for CMS = 1, and 2 cycles of CK8M for CMS = 0. Received data
is sampled in the middle of the data bit.
0x33
FE
0x33
WEMODE
0x34
YRCE
0x35
0x35
YPY[2:0]
Y input parity options.
YPY0 = 1 enable parity checking; 0 = disable.
YPY1 = 1 even parity; 0 = odd parity.
YPY2 = 1 bit 8; 0 = bit 15.
0x35
YCODEC
Y PCM input invert select (1 = inverted; 0 = noninverted).
Y input A-law/
μ
-law select.
Y input companded/linear select.
0x36
YULAW
0x36
YCOMP
0x36
EXY
Y input force parity error.
E input A-law/
μ
-law select.
E output companded/linear select.
0x36
EULAW
0x3A
ECOMP
0x3A
ECODEC
E output invert select (1 = inverted; 0 = noninverted).
E A-law/
μ
-law adjustment.
0x3A
EUAADJ
0x3A
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