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參數(shù)資料
| 型號： | TECO3264 |
| 廠商： | Lineage Power |
| 英文描述： | 32-Channel Echo Canceller(32通道回波清除器) |
| 中文描述： | 32通道回聲消除器（32通道回波清除器） |
| 文件頁數(shù)： | 126/128頁 |
| 文件大?。?/td> | 2328K |
| 代理商： | TECO3264 |
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
126
Lucent Technologies Inc.
Ordering Information
DS99-241PDH Replaces DS98-409TIC to Incorporate the Following Updates
1.
2.
3.
4.
5.
Throughout this data sheet, ehat and ê has been replaced by ê.
Page 11, Table 1, Pin Descriptions, pin 38 added to description that this pin must be held when not used.
Page 11, Table 1, Pin Descriptions, pin 25 corrected symbol name from RSTI to RST.
Page 15, Fast/Slow Convergence Control (F_CONV) section removed paragraph that does not apply.
Page 16, Table 2, Microprocessor Interface Control I/O, IntelMode column updated Address Latch Enable
(ALE) to active-low.
Page 16, Table 2, Microprocessor Interface Control I/O, IntelMode column updated Read Cycle (RD) to active-
low.
Page 18, Figure 5, MPIC Write Cycle (UP_MODE = 0) and Figure 6, MPIC Read Cycle (UP_MODE = 0) were
updated.
Page 28, Table 8, Programming Values (CET = Decimal) for [C, E]XBOFF, When CMS = 0 corrected heading
XRBOFF, YRBOFF to CRBOFF, ERBOFF.
Page 30, Figure 17, HSYNC, HDSP Relationship corrected 16
μ
s to 16 ms.
10. Page 47, Table 19, Parameter Address Map, updated bit 7 names of registers 7C, 7D, and 7F from spare to
HMODE, NMODE, and CENABLE, respectively.
11. Page 51, Table 20, Recommended Register Values for DS1 (μ-Law) and 2.048 Mbits/s Rate corrected recom-
mended values for register addresses 5C and 5D from 00 and 9F to 4C and 8A, respectively here and through-
out the document.
12. Page 52, Table 21, Recommended Register Values for E1 (A-Law), register address 21 corrected value from
0A to 02.
13. Page 84, Table 54, Low-Peak Count Register (03D) [84], updated the recommended values of bit 7—bit 2 to
100001 binary.
14. Page 84, Table 55, High-Peak Count Register (03E) [E3], updated the recommended values of bit 5—bit 0 to
100011 binary.
15. Page 90, Table 69, Noise Matching Enable Register (04C) [20] corrected recommended value and added table
on types of comfort noise that can be injected.
16. Page 94, Table 77, Variable Loss Noise Matching Select Register (054) [00] updated description of bit 6
VARLOSS.
17. Page 96, Table 81, Spectrally Matched Noise Matching Select Register (058) [B0] updated description of bit 7
USE_NM.
18. Page 104, Table 98, Fast Convergence Register (069) [60] and Table 99, Slow Convergence Gain Register
(06A) [40] removed Step: 0.2 dB from description.
19. Page 109, Table 109, Near-End Speech 1 Hangover Register (074) [FF], removed range and step information.
20. Page 112, Table 117, NLP Operate Time Double Register (07C) [A3] updated description of bit 7 HMODE.
21. Page 113, Table 119, Enable ê Threshold Register (07E) [18] and Table 120, Enable ê Threshold Register
(07F) [C0], updated bit symbol name from EETHO to EETHR in these tables and throughout the document.
22. Page 115, Table 122, Interupt Masks 1 Register (101), updated bit symbols ERRM2, ERRM3, and ERRM4 to
ERR2M, ERR3M, and ERR4M, respectively, in this table and throughout the document.
23. Page 123, Table 134, Output Signal Specification, outputs CPCM and EPCM (sinking and sourcing) currents
updated from (250 mA and 200 mA) to (0.25 mA and 0.2 mA), respectively.
24. Page 123, Table 134, Output Signal Specification, output D[0:7] (sinking and sourcing) currents updated from
(0.25 mA and 0.2 mA) to (10 mA and 8 mA), respectively.
25. Page 126, Ordering Information, updated Device Code from TECO3264 to TECO32642 and Comcode (Order-
ing Number) from 107956641 to 108194275, to reflect the version of the device.
6.
7.
8.
9.
Device Code
Package
Temperature
Comcode
(Ordering Number)
TECO32642-DB
160-Pin MQFPH
0
°
C to 85
°
C
108194275
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