參數(shù)資料
型號(hào)： TECO3264
廠商： Lineage Power
英文描述： 32-Channel Echo Canceller(32通道回波清除器)
中文描述： 32通道回聲消除器（32通道回波清除器）
文件頁(yè)數(shù)： 6/128頁(yè)
文件大小： 2328K
代理商： TECO3264
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Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
6
Lucent Technologies Inc.
List of Tables
(continued)
Tables
Page
Table 51. E Port Control 1 Register (03A) [F7 for DS1, F6 for E1]......................................................................... 82
Table 52. E Port Control 2 Register (03B) [08]....................................................................................................... 83
Table 53. Reserved (03C) [00]............................................................................................................................... 83
Table 54. Low-Peak Count Register (03D) [84]...................................................................................................... 84
Table 55. High-Peak Count Register (03E) [E3]..................................................................................................... 84
Table 56. Interval Count Register (03F) [E4].......................................................................................................... 85
Table 57. Good Intervals VPA Register (040) [00]................................................................................................. 85
Table 58. Good Intervals Declare Register (041) [70]............................................................................................ 85
Table 59. Phase Reversal Interval Minimum Register (042) [CA].......................................................................... 86
Table 60. Phase Reversal Interval Maximum Register (043) [8A].......................................................................... 86
Table 61. Tone Detector Declarations Register (044) [AC].................................................................................... 87
Table 62. Low Voice Path Assurance (VPA) Count Register (045) [5F] ................................................................ 87
Table 63. High VPA Count Register (046) [22]....................................................................................................... 88
Table 64. VPA Power Minimum Register (047) [0C] .............................................................................................. 88
Table 65. Tone Detector Power Minimum Register (048) [0E]............................................................................... 88
Table 66. Phase Reversal Interval Maximum Register (049) [4D] ......................................................................... 89
Table 67. Tone Detector Threshold Register (04A) [90]......................................................................................... 89
Table 68. Y Energy Threshold Register (04B) [7F] ................................................................................................ 90
Table 69. Noise Matching Enable Register (04C) [20]........................................................................................... 90
Table 70. Near-End Speech Hangover Register (04D) [F0]................................................................................... 91
Table 71. ê Noise Floor Estimate Maximum 1 Register (04E) [1F]........................................................................ 91
Table 72. ê Noise Floor Estimate Maximum 2 Register (04F) [00]......................................................................... 92
Table 73. Gamma ê Noise Floor Register (050) [02].............................................................................................. 92
Table 74. Clamp ê Noise Floor 1 Register (051) [FF]............................................................................................. 92
Table 75. Clamp ê Noise Floor 2 Register (052) [3F]............................................................................................. 93
Table 76. Noise Floor Estimate High Hysteresis Threshold 1 Register (053) [00] ................................................. 93
Table 77. Variable Loss Noise Matching Select Register (054) [00]...................................................................... 94
Table 78. Noise Floor Estimate Low Hysteresis Threshold Register (055) [08]..................................................... 94
Table 79. NLP Freeze, Soft NLP Select Register (056) [80].................................................................................. 95
Table 80. Noise Floor Estimate Register (057) [21] ............................................................................................... 95
Table 81. Spectrally Matched Noise Matching Select Register (058) [B0]............................................................. 96
Table 82. Soft NLP Number Interval Time Steps 1 Register (059) [08].................................................................. 96
Table 83. Soft NLP Number Interval Time Steps 2 Register (05A) [00]................................................................. 97
Table 84. Soft NLP Interval Steps Register (05B) [20]........................................................................................... 97
Table 85. Loss Increment Attenuated ê 1 Register (05C) [4C]............................................................................... 98
Table 86. Loss Increment Attenuated ê 2 Register (05D) [8A]............................................................................... 98
Table 87. ê Zero Crossing Threshold Register (05E) [00]...................................................................................... 99
Table 88. Soft NLP Incremental Loss Factor 1 Register (05F) [00]........................................................................ 99
Table 89. Soft NLP Incremental Loss Factor 2 Register (060) [1E] ..................................................................... 100
Table 90. Reserved Register (061) [00] ............................................................................................................... 100
Table 91. State Variable Test 1 Register (062) [00]............................................................................................. 100
Table 92. State Variable Test 2 Register (063) [00]............................................................................................. 101
Table 93. State Variable Test 3 Register (064) [00]............................................................................................. 101
Table 94. Convolution Update Processor Disable Register (065) [00]................................................................. 101
Table 95. Test Control Register (066) [00]........................................................................................................... 102
Table 96. X and Y Loss Pads Register (067) [00]................................................................................................ 102
Table 97. E and Y Exponentially Mapped (EMP) Filter Time Constant Register (068) [01]................................. 103
Table 98. Fast Convergence Register (069) [60] ................................................................................................. 104
Table 99. Slow Convergence Gain Register (06A) [40]........................................................................................ 104
Table 100. Fast Convergence Beta 1 Register (06B) [12].................................................................................... 104
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