參數(shù)資料
型號: TECO3264
廠商: Lineage Power
英文描述: 32-Channel Echo Canceller(32通道回波清除器)
中文描述: 32通道回聲消除器(32通道回波清除器)
文件頁數(shù): 78/128頁
文件大?。?/td> 2328K
代理商: TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
78
Lucent Technologies Inc.
Register Architecture
(continued)
Page 0 Read/Write Registers 000
07FE
(continued)
Y-E Bulk Time-Slot Offset Register
Table 42. Y-E Bulk Time-Slot Delay Register (031) [15]
X Input Format Register
Table 43. X Input Format Register (032) [02]
Edge Sampling Register
Table 44. Edge Sampling Register (033) [02]
Bit
4—0
Symbol
YDLY[4:0]
Parameter Name and Description
Y-E Time-Slot Delay[4:0].
Determines the number of time slots of delay between the Y
input and the E output. 00000 = no delay; 11111 = 31 time slots of delay.
Recommended value = 10101 or 21 time slots.
Reserved.
Set to 0.
7—5
Bit
0
Symbol
EX
Parameter Name and Description
Exercise Parity Error.
0 = Parity error is disabled [recommended value].
1 = Parity error is enabled.
X Input Data Format.
Selects either companded (A-law or
μ
-law) or linear data on the X
input.
1
XCOMP
0 = X linear code.
1 = X companded code [recommended value].
Reserved.
Set to 0.
7—2
Bit
0
Symbol
EET
Parameter Name and Description
Enable Edge Transfer.
Allows the sync pulse to be shifted by one edge of the 8 MHz
clock (CK8M).
0 = No shift is performed [recommended value].
1 = Shift enabled.
Frame Edge.
Allows the flexibility to sample the SYNC pulse on either rising or falling
edge of 8 MHz clock (CK8M).
1
FE
0 = Sample at the negative-going/falling edge of the clock pulse.
1 = Sample at the positive-going/rising edge of the clock pulse [recommended value].
Reserved.
Set to 0.
7—2
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