參數(shù)資料
型號(hào): TECO3264
廠商: Lineage Power
英文描述: 32-Channel Echo Canceller(32通道回波清除器)
中文描述: 32通道回聲消除器(32通道回波清除器)
文件頁數(shù): 65/128頁
文件大?。?/td> 2328K
代理商: TECO3264
Data Sheet
August 1999
TECO3264 32-Channel Echo Canceller
65
Lucent Technologies Inc.
Register Architecture
(continued)
Page 0 Read/Write Registers 000
07FE
Per-Channel Control Parameters
Table 16 lists the parameters in registers 000—01F for which each channel has independent control. For each
function, there are 32 bits corresponding to the 32 channels processed by the chip. The first 32 bytes in the mem-
ory map are referred to as the channel control words and the address corresponds to the time slot that the word
controls.
Register addresses:
000 to 01F
. 00 = channel 0, 1F = channel 31. The recommended value is
00
.
Table 24. Per-Channel Control Parameters
Bit
Symbol
DEC
Parameter Name and Description
0
Disable Echo Canceller.
Per-channel disable of echo canceller (EC) for channels 0 to
31. DEC overrides all automatic EC disable options (typically those that operate on the
detection of a FAX or modem tone).
0 = Enable normal echo cancellation operation [recommended value].
1 = Disable echo cancellation.
Clear Enable.
Per-channel 64-clear mode, also called bypass (BP) mode, enable for
time slots 0 to 31. Clear enable overrides
all
other per-channel provisions for the given
channel. The 64 kbits/s DS0 channel is passed unchanged from the X/receive-in port to
the C/receive-out port and from the Y/send-in port to the E/send-out port. If set, the high-
pass filters in X and Y are removed to preserve digital signal integrity. The registers for
the eight unused channels for DS1 applications may be set to 64 clear/bypass mode with
clear enable, register = 02 for the given channels. Another example is 64 clear to pass an
E1 common signaling channel.
1
EBP
0 = Disable 64-clear channel (bypass) [recommended value].
1 = Enable 64-clear channel.
Enable Nonlinear Processor.
Per-channel full-time enable of the nonlinear processor
for time slots 0 to 31.Output of E port is set to silence. ENLP has the highest precedence
over any of the automatic NLP options built into the chip. See parameter MNLPINT, regis-
ter 022, bit 0, for more information on NLP control.
2
ENLP
0 = Normal nonlinear processing operation [recommended value].
1 = Enable full-time nonlinear processing.
H-Register Reset.
Per-channel H-register reset for time slots 0 to 31. Taps are set to
zero.
3
HRST
0 = Normal operation [recommended value].
1 = Reset H-register and X-register taps to zero.
H-Register Freeze.
Per-channel H-register freeze for time slots 0 to 31. Taps are held at
current value.
4
HFRZ
0 = Do not freeze H-register tap values (normal operation-permit updates) [recommended
value].
1 = Freeze H-register tap values (inhibit updates).
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